IP Library Granted Patent US 12,417,053
Granted Patent B2
US 12,417,053 · App. 18/376,122 · Granted Sep 16, 2025

Data storage device and method for delaying execution of a host write command to perform an internal memory operation

Inventors: Amit Sharma (Bangalore, IN); Dinesh Kumar Agarwal (Bangalore, IN)
Assignee: Sandisk Technologies, Inc.
G06F3/0659G06F3/0604G06F3/064G06F3/0679
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Quick Facts
Patent No.
US 12,417,053
App. No.
18/376,122
Granted
Sep 16, 2025
Kind
B2
Abstract

A data storage device and method for delaying execution of a host write command to perform an internal memory operation. In one embodiment, a data storage device is provided comprising a memory with single-level cell (SLC) blocks and multi-level cell (MLC) blocks, as well as a controller. The controller is configured to store, in a queue, a plurality of write commands received from a host, wherein each write command is associated with a timeout window; determine how long each of the plurality of write commands has been pending in the queue; and for each write command, delay execution of the write command within the write command's timeout window until the write command has been pending in the queue for a specified amount of time, wherein delaying execution of each write command provides the controller with time to perform a memory operation to increase an amount of available SLC blocks in the memory. Other embodiments are provided.

Claims (32)

1. A data storage device comprising:

a memory comprising single-level cell (SLC) blocks and multi-level cell (MLC) blocks; and

a processor configured to communicate with the memory and further configured to:

store, in a queue, a plurality of sequential write commands and a non-sequential write command received from a host, wherein each sequential write command of the plurality of sequential write commands is associated with a timeout window and execution of the plurality of sequential write commands consumes available SLC blocks in the memory, and wherein the timeout window is smaller than a timeout window for the non-sequential write command;

determine how long each of the plurality of sequential write commands has been pending in the queue; and

for each sequential write command of the plurality of sequential write commands, delay execution of the sequential write command within the sequential write command's timeout window until the sequential write command has been pending in the queue for a specified amount of time, wherein delaying execution of each sequential write command of the plurality of sequential write commands provides the processor with time to perform a memory operation to increase an amount of available SLC blocks in the memory.

2. The data storage device of claim 1 , wherein the processor is further configured to dynamically vary the specified amount of time based on a current amount of available SLC blocks in the memory.

3. The data storage device of claim 1 , wherein the processor is further configured to prioritize at least one sequential write command of the plurality of sequential write commands over another sequential write command of the plurality of sequential write commands based on a prioritization factor.

4. The data storage device of claim 3 , wherein the prioritization factor comprises a device type.

5. The data storage device of claim 3 , wherein the prioritization factor comprises a partition type.

6. The data storage device of claim 3 , wherein the prioritization factor comprises a queue type.

7. The data storage device of claim 3 , wherein the prioritization factor 7 , comprises a command type.

8. The data storage device of claim 1 , wherein the processor is further configured to use a timer to determine how long each sequential write command of the plurality of sequential write commands has been pending in the queue.

9. The data storage device of claim 1 , wherein the processor is further configured to determine how long each sequential write command of the plurality of sequential write commands has been pending in the queue by maintaining a counter of how many operations were issued within the data storage device since each sequential write command of the plurality of sequential write commands was received.

10. The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.

11. A method comprising:

performing in a data storage device comprising a memory:

storing, in a queue, a plurality of sequential write commands and a non-sequential write command received from a host, wherein each sequential write command of the plurality of sequential write commands is associated with a duration limit, and wherein the duration limit is less than a duration limit for the non-sequential write command;

determining how long each of the plurality of sequential write commands has been pending in the queue; and

for each sequential write command of the plurality of sequential write commands, delaying execution of the sequential write command within the sequential write command's duration limit until the sequential write command has been pending in the queue for a threshold amount of time.

12. The method of claim 11 , further comprising dynamically changing the threshold amount of time based on an available amount of single-level cell (SLC) blocks in the memory.

13. The method of claim 11 , further comprising prioritizing at least one sequential write command of the plurality of sequential write commands over another sequential write command of the plurality of sequential write commands based on a prioritization factor.

14. The method of claim 13 , wherein the prioritization factor comprises a device type.

15. The method of claim 13 , wherein the prioritization factor comprises a partition type.

16. The method of claim 13 , wherein the prioritization factor comprises a queue type.

17. The method of claim 13 , wherein the prioritization factor comprises a command type.

18. The method of claim 11 , further comprising using a timer to determine how long each sequential write command of the plurality of sequential write commands has been pending in the queue.

19. The method of claim 11 , further comprising determining how long each sequential write command of the plurality of sequential write commands has been pending in the queue by maintaining a counter of how many operations were issued within the data storage device since each sequential write command of the plurality of sequential write commands was received.

20. A data storage device comprising:

a memory;

means for storing, in a queue, a plurality of sequential write commands and a non-sequential write command received from a host, wherein each sequential write command of the plurality of sequential write commands is associated with a timeout window, and wherein the timeout window is smaller than a timeout window for the non-sequential write command;

means for delaying execution of each sequential write command of the plurality of sequential write commands within the sequential write command's timeout window until the sequential write command has been pending in the queue for a specified amount of time.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2023
From: SHARMA, AMIT; AGARWAL, DINESH KUMAR
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 065109/0363 →
Continuity (1)
Related Publication 20250110666A1 · Apr 3, 2025
References Cited (13)
US 5559988A · Durante et al. · 1996 [cited by applicant]
US 9753653B2 · Ellis et al. · 2017 [cited by applicant]
US 9778878B2 · Hodgdon et al. · 2017 [cited by applicant]
US 10545834B1 · Smith · 2020 [cited by examiner]
US 11494122B2 · Tsai et al. · 2022 [cited by applicant]
US 20100082879A1 · McKean et al. · 2010 [cited by applicant]
US 20180183724A1 · Callard · 2018 [cited by examiner]
US 20190294371A1 · Lee · 2019 [cited by examiner]
US 20200304238A1 · Xiao · 2020 [cited by examiner]
US 20220245006A1 · Kommalapati · 2022 [cited by examiner]
US 20230176778A1 · Gohain · 2023 [cited by examiner]
“Information technology—SCSI Architecture Model—5 (SAM-5)”; Working Draft American National Standard; Project T10/BSR INCITS 515; Revision 21; Jul. 22, 2015. [cited by applicant]
TPAR4144—Command Duration Limits (CDL); NVMe Technical Proposal Authorization Request; NVM Express; Aug. 9, 2022; 2 pages. [cited by applicant]