Non-volatile memory and method for power efficient read or verify using lockout control
View Patent ↗Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.
1. A method of sensing a page of memory cells in an array, wherein each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states, comprising:
providing a first series of one or more demarcation threshold voltages for demarcating between memory states in a first page read discerning a first bits of the page of memory cells, the first page read selected from a group consisting of a lower page read and a middle page read;
identifying one or more sets of memory cells demarcated between the one or more demarcation threshold voltages of the first series in the first page read;
providing a second series of one or more demarcation threshold voltages for demarcating between memory states in a second page read discerning a second bits of the page of memory cells, the second page read selected from a group consisting of the middle page read and a upper page read, the second page read is different than the first page read;
inhibiting conduction currents of the one or more sets of memory cells identified by the first series from the first page read, wherein the conduction currents are inhibited during the second series of the one or more demarcation threshold voltages in the second page read; and
identifying one or more sets of memory cells demarcated between the one or more demarcation threshold voltages of the second series in the second page read.
2. The method of claim 1 , wherein the one or more sets of memory cells demarcated between the one or more demarcation threshold voltages of the first series are identified by sensing a high conduction current.
3. The method of claim 1 , wherein the multiple memory states are eight or more memory states.
4. The method of claim 1 , wherein the conduction currents of the one or more sets of memory cells are inhibited by grounding bit lines coupled to the inhibited one or more sets of memory cells.
5. The method of claim 1 , wherein the one or more sets of memory cells identified by the first series of demarcation threshold voltages and wherein the one or more sets of memory cells identified by the second series of demarcation threshold voltages are part of a read operation.
6. The method of claim 1 , wherein the one or more sets of memory cells identified by the first series of demarcation threshold voltages and wherein the one or more sets of memory cells identified by the second series of demarcation threshold voltages are part of a program-verify operations.
7. A method of sensing a page of memory cells in an array, wherein each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states, comprising:
conducting a lower page read of one or more demarcation threshold voltages of the page of memory cells;
conducting a middle page read of one or more demarcation threshold voltages of the page of memory cells, wherein memory cells identified from the lower page read are selectively locked out during the middle page read; and
conducting an upper page read of one or more demarcation threshold voltages of the page of memory cells, wherein memory cells identified from a prior page read are selectively locked out during the upper page read.
8. The method of claim 7 , wherein the selective locked out memory cells identified from the prior page read are identified from the lower page read.
9. A method of sensing a plurality of memory cells in an array, wherein each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states, comprising:
conducting a lower page read of one or more demarcation threshold voltages;
conducting a middle page read of one or more demarcation threshold voltages, wherein memory cells identified from the lower page read are selectively locked out during the middle page read; and
conducting an upper page read of one or more demarcation threshold voltages, wherein memory cells identified from a prior page read are selectively locked out during the upper page read, wherein the selective locked out memory cells identified from the prior page read are identified from the middle page read.
10. A method of sensing a plurality of memory cells in an array, wherein each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states, comprising:
conducting a lower page read of one or more demarcation threshold voltages;
conducting a middle page read of one or more demarcation threshold voltages, wherein memory cells identified from the lower page read are selectively locked out during the middle page read; and
conducting an upper page read of one or more demarcation threshold voltages, wherein memory cells identified from a prior page read are selectively locked out during the upper page read, wherein the selective locked out memory cells identified from the prior page read are identified from the lower page read and the middle page read.
11. A method of sensing a plurality of memory cells in an array, wherein each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states, comprising:
conducting a lower page read of one or more demarcation threshold voltages;
conducting a middle page read of one or more demarcation threshold voltages, wherein memory cells identified from the lower page read are selectively locked out during the middle page read; and
conducting an upper page read of one or more demarcation threshold voltages, wherein memory cells identified from a prior page read are selectively locked out during the upper page read, wherein the memory cells are selectively locked out during the middle page read and during the upper page read out by selectively inhibiting a conduction current of the memory cells.
12. A method of sensing a plurality of memory cells in an array, wherein each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states, comprising:
conducting a lower page read of one or more demarcation threshold voltages;
conducting a middle page read of one or more demarcation threshold voltages, wherein memory cells identified from the lower page read are selectively locked out during the middle page read; and
conducting an upper page read of one or more demarcation threshold voltages, wherein memory cells identified from a prior page read are selectively locked out during the upper page read, wherein the memory cells are selectively locked out during the middle page read and during the upper page read out by selectively grounding their bit lines.
13. A memory device, comprising;
a page of memory cells accessible by a plurality of bit lines and a plurality of word lines;
a plurality of sensing circuits sensing conduction current in a portion of the page of memory cells in a current page read to determine a first bits of the page of memory cells; and
a bit-line grounding circuit for each sensing circuit to ground associated bit lines to the portion of the plurality of memory cells during a subsequent page read of the page of memory cells to determine a second bits of the page of memory cells.
14. The memory device of claim 13 , wherein a series of demarcation threshold voltages are supplied over multiple read pages.
15. The memory device of claim 13 , wherein each memory cell may store a charge level corresponding to eight or more memory states.
16. The memory device of claim 13 , wherein each memory cell may store at least three bits of data.
17. The memory device of claim 13 , wherein the memory cells are configured in a NAND configuration.
18. The memory device of claim 13 , wherein the associated bit lines to the portion of the page of memory cells determined in the current page read are grounded to inhibit conduction currents during the subsequent page read of the page of memory cells.
19. A memory device, comprising;
a page of memory cells accessible by a plurality of bit lines and a plurality of word lines, wherein each memory cell may store a charge level corresponding to eight or more memory states;
a sensing means operable to perform a lower page read, a middle page read, and an upper page read; and
a lockout means operable to lockout a portion of the memory cells during a current page read selected from a group consisting of the middle page read and the upper page read, the portion of the memory cells identified from a prior page read selected from a group consisting of the lower page read and the middle page read, the prior page read is different than the current page read.
20. The memory device of claim 19 , wherein the current page read is the middle page read and the prior page read is the lower page read.
21. The memory device of claim 19 , wherein the current page read is the upper page read and the prior page read is the lower page read.
22. The memory device of claim 19 , wherein the lock means reduces current consumption.
23. A memory device, comprising;
an array of memory cells accessible by a plurality of bit lines and a plurality of word lines, wherein each memory cell may store a charge level corresponding to eight or more memory states;
a sensing means operable to perform a lower page read, a middle page read, and an upper page read; and
a lockout means operable to lockout a portion of the memory cells during a current page read, the portion of the memory cells identified from a prior page read, wherein the current page read is the upper page read and the prior page read is the middle page read.
24. A memory device, comprising;
an array of memory cells accessible by a plurality of bit lines and a plurality of word lines, wherein each memory cell may store a charge level corresponding to eight or more memory states;
a sensing means operable to perform a lower page read, a middle page read, and an upper page read; and
a lockout means operable to lockout a portion of the memory cells during a current page read, the portion of the memory cells identified from a prior page read, wherein the current page read is the upper page read and the prior page read is both the lower page read and the middle page read.