Failure mode study based error correction
A method for error correction in a memory system includes determining a bit error ratio for a memory block of the memory system during a read operation. The method further includes determining whether the bit error ratio is between a first threshold and a second threshold. The method further includes based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a select gate drain (SGD) read operation on a SGD word line of the memory block. The method further includes generating first soft bit data using SGD data corresponding to the SGD read operation. The method further includes performing a low-density parity-check correction using the first soft bit data on the memory block.
1. A method for error correction in a memory system, the method comprising:
determining a bit error ratio for a memory block of the memory system during a read operation;
determining whether the bit error ratio is between a first threshold and a second threshold;
based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a select gate drain (SGD) read operation on a SGD word line of the memory block;
generating first soft bit data using SGD data corresponding to the SGD read operation;
performing a low-density parity-check correction using the first soft bit data on the memory block; and
based on a determination that the bit error ratio is above a third threshold that is greater than the second threshold, performing a low-density parity-check correction on the memory block using third soft bit data, different from the first soft bit data.
2. The method of claim 1 , wherein the first threshold includes 80 bit errors per 4 KB bits read and the second threshold includes 250 bit errors per 4 KB read.
3. The method of claim 1 , wherein the first soft bit data includes a logical NOT of the SGD data.
4. The method of claim 1 , wherein the SGD word line is common to all word lines in the memory block.
5. The method of claim 1 , wherein the bit error ratio is between the second threshold and a third threshold.
6. The method of claim 5 , further comprising, generating second soft bit data using the first soft bit data and word line soft bit data of the memory block.
7. The method of claim 6 , further comprising, performing a low-density parity-check correction using the second soft bit data on the memory block.
8. A memory system comprising:
a non-volatile storage having an array of memory blocks storing data; and
a controller in communication with the memory blocks, the controller configured to:
determine a bit error ratio for a memory block of the array of memory blocks during a read operation;
determine whether the bit error ratio is between a first threshold and a second threshold;
based on a determination that the bit error ratio is between the first threshold and the second threshold, perform a select gate drain (SGD) read operation on a SGD word line of the memory block;
generate first soft bit data using SGD data corresponding to the SGD read operation;
perform a low-density parity-check correction using the first soft bit data on the memory block; and
based on a determination that the bit error ratio is above a third threshold that is greater than the second threshold, perform a low-density parity-check correction on the memory block using third soft bit data, different from the first soft bit data.
9. The system of claim 8 , wherein the first threshold includes 80 bit errors per 4 KB read bits and the second threshold includes 250 bit errors per 4 KB read.
10. The system of claim 8 , wherein the first soft bit data includes a logical NOT of the SGD data.
11. The system of claim 8 , wherein the SGD word line is common to all word lines in the memory block.
12. The system of claim 8 , wherein the bit error ratio is between the second threshold and a third threshold.
13. The system of claim 12 , wherein the controller is further configured to generate second soft bit data using the first soft bit data and word line soft bit data of the memory block.
14. The system of claim 13 , wherein the controller is further configured to perform a low-density parity-check correction using the second soft bit data on the memory block.
15. A method for operating a memory system having a controller and blocks of memory, the method comprising:
determining a bit error ratio for a memory block of the memory system during a read operation;
determining whether the bit error ratio is between a first threshold and a second threshold;
based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a low-density parity-check correction on the memory block using first soft bit data;
based on a determination that the bit error ratio is between the second threshold and a third threshold, performing a low-density parity-check correction on the memory block using second soft bit data; and
based on a determination that the bit error ratio is above the third threshold, performing a low-density parity-check correction on the memory block using third soft bit data, wherein the third soft bit data is different from the first soft bit data.
16. The method of claim 15 , wherein the first threshold includes 80 bit errors per 4 KB read, the second threshold includes 250 bit errors per 4 KB read, and the third threshold includes 530 bit errors per 4 KB read.
17. The method of claim 15 , further comprising, based on a determination that the bit error ratio corresponds to bit errors caused by weak word line-word line shorts, generating word line short data.
18. The method of claim 17 , further comprising, generating fourth soft bit data using the word line short data and performing a low-density parity-check on the memory block using the fourth soft bit data.