Granted Patent B2

US 10,860,477 · App. 15/716,467 · Granted Dec 8, 2020

Inventors: Frank R. Chu (Milpitas, CA); Luiz M. Franca-Neto (Sunnyvale, CA); Timothy K. Tsai (Santa Clara, CA); Qingbo Wang (Irvine, CA)

Assignee: WESTERN DIGITAL TECNOLOGIES, INC.

G06F12/06G06F12/0223G06F12/0238G11C11/005G06F2212/205G06F2212/2022G06F2212/2024Y02D10/00

Abstract

Claims (25)

1. An apparatus, comprising:

a direct access storage device (DASD);

a direct attached dual in line memory (DIMM) card, wherein the DIMM card is separate from the storage; wherein the DIMM card includes:

at least one memory unit of dynamic random access memory;

at least one nonvolatile memory including:

a NAND flash memory,

a resistive RAM memory,

a spin transfer torque RAM memory, and

Phase Change memory (PCM);

at least one processing unit;

a memory containing a control code for access by the at least one processing unit;

at least one memory electrical interface circuit; and

at least one enhanced storage class memory (eSCM) interface configured to interface with the DASD; and

an eSCM controller coupled to both the DASD and the DIMM card and configured to control operations of the at least one nonvolatile memory, and wherein the apparatus is configured to transfer data between the DASD and the DIMM, and within the at least one nonvolatile memory without a host CPU intervention, wherein the eSCM controller is configured to continue to write data to the NAND flash memory, wherein the data is selectively migrated among the PCM, the resistive RAM memory, and the spin transfer torque RAM memory, wherein the eSCM is configured to straddle data sets across the DASD and the at least one nonvolatile memory, and wherein the data sets are expected to be read as a single set.

2. The apparatus according to claim 1 , further comprising:

at least one bus interface.

3. The apparatus according to claim 2 , wherein the bus interface is configured as one of a standard dynamic random access memory bus and a fully-buffered dynamic random access memory bus.

4. The apparatus according to claim 1 , wherein the at least one processing unit is configured to determine when data should be stored in dynamic random access memory, phase-change memory, resistive random access memory, spin-transfer-torque ram memory and NAND flash memory.

5. The apparatus according to claim 1 , wherein the at least one processing unit is configured to determine when data should be stored in dynamic random access memory, phase-change memory, resistive random access memory, spin-transfer-torque ram memory and NAND flash memory based on a size of a data set.

6. A method for operating a direct attached dual in line memory (DIMM) card, comprising:

buffering a set of data in a dynamic random access memory;

writing the set of data into a NAND flash memory; and

selectively migrating the set of data from the NAND flash memory to phase change memory, resistive random access memory, and spin-torque transfer random access memory based on a size of the set of data through an enhanced storage class memory (eSCM) controller configured to control operations of a storage class memory, wherein the set of data is transferred through at least one eSCM interface configured to interface with both the direct attached dual in line memory (DIMM) card and a direct access storage device (DASD) without interference from a host, wherein the eSCM controller is configured to continue to write data to the NAND flash memory, wherein the data is selectively migrated among the phase change memory, the resistive random access memory, and the spin transfer torque random access memory, wherein the eSCM is configured to straddle data sets across the DASD and the DIMM, and wherein the data sets are expected to be read as a single set.

7. The method according to claim 6 , further comprising:

reading data from at least one of the dynamic random access memory, a phase-change memory, a resistive random access memory, a spin-torque transfer random access memory and the NAND flash memory.

Assignments (11)