Memory array having memory cells formed from metallic material
View Patent ↗Solid-state memories are disclosed that are comprised of cross-point memory arrays. The cross-point memory arrays include a first plurality of electrically conductive lines and a second plurality of electrically conductive lines that cross over the first plurality of electrically conductive lines. The memory arrays also include a plurality of memory cells located between the first and second conductive lines. The memory cells are formed from a metallic material, such as FeRh, having the characteristic of a first order phase transition due to a change in temperature. The first order phase transition causes a corresponding change in resistivity of the metallic material.
1. A memory array comprising:
a plurality of word lines;
a plurality of bit lines; and
a plurality of memory cells located at the intersections of the word lines and the bit lines;
wherein the memory cells consist of a single layer of a metallic alloy, wherein the metallic alloy comprises Fe and Rh.
2. The memory array of claim 1 wherein the magnetic alloy exhibits a first order phase transition from a low temperature high resistivity state to a high temperature low resistivity state.
3. The memory array of claim 1 wherein the metallic alloy comprises FeRh.
4. The memory array of claim 1 wherein the metallic alloy further comprises one of Ir, Pt, Pd, or Ni.
5. A memory array comprising:
a first plurality of electrically conductive lines;
a second plurality of electrically conductive lines that cross over the first plurality of electrically conductive lines at intersection regions; and
a plurality of memory cells located at the intersection regions between the first plurality of electrically conductive lines and the second plurality of electrically conductive lines;
wherein the memory cells consist of a single layer of a metallic alloy, wherein the metallic alloy comprises at least Fe and Rh.
6. The memory array of claim 5 wherein a characteristic of the metallic alloy includes a first order phase transition due to a temperature change and substantially completing the transition in the range of about 20° C. or less.
7. The memory array of claim 6 wherein the first order phase transition is from a low temperature high resistivity state to a high temperature low resistivity state.
8. The memory array of claim 5 wherein the metallic alloy further includes one of Ir, Pt, Pd, or Ni.
9. A memory array comprising:
a first plurality of electrically conductive lines;
a second plurality of electrically conductive lines that cross over the first plurality of electrically conductive lines; and
a plurality of memory cells between the first plurality of electrically conductive lines and the second plurality of electrically conductive lines, wherein each of the plurality of memory cells contacts one of the first plurality of electrically conductive lines and contacts one of the second plurality of electrically conductive lines;
wherein the memory cells consist entirely of a metallic alloy, wherein the metallic alloy comprises Fe and Rh.
10. The memory array of claim 9 wherein the metallic alloy exhibits a first order phase transition due to a temperature change in the range of about 20° C. or less.
11. The memory array of claim 10 wherein the first order phase transition is from a low temperature high resistivity state to a high temperature low resistivity state occurring at a transition temperature.
12. The memory array of claim 11 wherein the transition temperature is increased by doping the metallic alloy with one of Jr or Pt.
13. The memory array of claim 11 wherein the transition temperature is decreased by doping the metallic alloy with one of Pd or Ni.
14. The memory array of claim 10 wherein the first order phase transition is from an antiferromagnetic phase to a ferromagnetic phase.
15. The memory array of claim 9 wherein the memory cell is comprised entirely of FeRh.