Data address management in non-volatile memory
A method, an apparatus, and a system for data address management in non-volatile memory. Write data is allocated to each of a plurality of multi-level pages configured for storage on a page of a non-volatile memory array. A digest is associated with the write data of one multi-level page based on an attribute for that multi-level page. This attribute differs from the attributes of at least one of the other multi-level pages. An amount of redundancy data to be stored with write data on the multi-level page is reduced to account for the associated digest. A digest may be distributed among a plurality of ECC codewords of a multi-level page. The reduced redundancy data, the digest, and the write data for the multi-level page are stored on the page along with the write data for each of the other multi-level pages of the plurality of multi-level pages.
1. A method, comprising:
allocating write data to each of a plurality of multi-level pages configured for storage on a page of a non-volatile memory array;
associating a digest with write data of one multi-level page of the plurality of multi-level pages corresponding to an attribute of the one multi-level page, the attribute different from attributes of at least one mufti-level page of the plurality of multi-level pages;
reducing an amount of redundancy data configured to be stored with write data on the one multi-level page to account for the associated digest;
combining the digest with a header for an ECC codeword configured to include the header, write data, and the reduced redundancy data;
reducing the reduced redundancy data by an amount equal to a size of the digest; and
storing the reduced redundancy data, the digest, and the write data of the one multi-level page on the page along with the write data for each other multi-level page of the plurality of multi-level pages.
2. The method of claim 1 , further comprising generating the digest that comprises address information for the write data of each other mufti-level page of the plurality of mufti-level pages.
3. The method of claim 2 , wherein the address information comprises a logical group identifier and a logical group offset configured together to uniquely identify a subset of the write data.
4. The method of claim 2 , wherein the digest comprises address information for the write data of the one multi-level page and the digest also comprises header metadata for the write data of each other multi-level page of the plurality of multi-level pages.
5. The method of claim 1 , further comprising:
generating a first ECC codeword that includes the reduced redundancy data, address information for the write data of the one multi-level page, and a digest comprising address information for the write data of the plurality of multi-level pages; and
generating a plurality of ECC codewords for the write data of each other multi-level page of the plurality of multi-level pages; the plurality of ECC codewords each comprising more redundancy data than the first ECC codeword.
6. The method of claim 1 , wherein the one multi-level page includes address information for the write data of the one multi-level page, the method further comprising:
reading data of the one multi-level page without reading data of the other multi-level pages of the plurality of multi-level pages; and
parsing the data of the one multi-level page to determine address information for the write data of the one multi-level page and to determine the digest comprising address information for write data of each other multi-level page of the plurality of multi-level pages.
7. The method of claim 1 , further comprising:
omitting address information associated with write data configured to be stored on another multi-level page based on the attribute for the other multi-level page;
increasing an amount of redundancy data configured to be stored with the write data of the other multi-level page to account for the omitted address information; and
storing the increased redundancy data and the write data of the other multi-level page on the page along with the write data for each other multi-level page of the plurality of multi-level pages.
8. The method of claim 1 , wherein the attribute comprises a reliability attribute based on a multi-level storage cell encoding configured to define the plurality of multi-level pages within the page such that the reliability attribute of the one multi-level page is greater than reliability attributes of each other multi-level page of the plurality of multi-level pages.
9. The method of claim 8 , wherein the multi-level storage cell encoding defines one memory state transition for a lower multi-level page, two memory state transitions for a middle multi-level page, six memory state transitions for an upper multi-level page, and six memory state transitions for a top multi-level page.
10. The method of claim 8 , wherein the multi-level storage cell encoding defines one memory state transition for a lower multi-level page, two memory state transitions for a middle multi-level page, four memory state transitions for an upper multi-level page, and eight memory state transitions for a top multi-level page.
11. The method of claim 8 , wherein the mufti-level storage cell encoding defines two memory state transitions for a lower multi-level page, three memory state transitions for a middle multi-level page, five memory state transitions for an upper multi-level page, and five memory state transitions for a top multi-level page.
12. The method of claim 1 , wherein the attribute comprises a lower bit error rate for the one multi-level page than bit error rates for each other multi-level page of the plurality of multi-level pages.
13. The method of claim 1 , wherein the attribute comprises a type of the one multi-level page and the type comprises one of a lower multi-level page, a middle multi-level page, an upper multi-level page, and a top multi-level page.
14. The method of claim 1 ; wherein the digest comprises a set of digests, each member of the set of digests included within a flash management unit stored on the one multi-level page.
15. An apparatus, comprising:
a non-volatile memory array comprising Quad-level Cell (QLC) NAND flash memory cells configured to store a lower multi-level page, a middle multi-level page, an upper multi-level page, and a top multi-level page;
wherein the lower multi-level page has higher data integrity than the middle multi-level page, the upper multi-level page, and the top multi-level page;
a multi-level page allocator configured to assign data blocks to each of the lower multi-level page; the middle multi-level page, the upper multi-level page, and the top multi-level page, the data blocks comprising write data for a set of write commands;
an address allocator configured to determine address information for the assigned data blocks;
a header generator configured to:
generate headers for flash management units (FMUs) that include the assigned data blocks, the headers comprising the determined address information;
generate a digest comprising address information for FMUs assigned to the middle multi-level page, the upper multi-level page, and the top multi-level page; and
combine the digest with at least one FMU assigned to the lower multi-level page;
an error correction code encoder configured to:
generate ECC codewords for each FMU assigned to the middle multi-level page, the upper multi-level page, and the top multi-level page;
generate a lower page ECC codeword for each FMU assigned to the lower multi-level page;
wherein at least one lower page ECC codeword comprises redundancy data reduced in size proportional to a size of the digest of an associated FMU; and
a read/write circuit configured to:
store the ECC codewords within the middle multi-level page, the upper multi-level page, and the top multi-level page and the lower page ECC codeword to the lower multi-level page of a page of the non-volatile memory array.
16. The apparatus of claim 15 , wherein the error correction code encoder is configured such that each ECC codeword and lower page ECC codeword is the same size.
17. A system, comprising:
a non-volatile memory array comprising Quad-level Cell (QLC) NAND flash memory cells; and
a storage controller comprising:
a flash translation layer configured to:
associate write data of a plurality of write commands with multi-level pages of QLC memory cells, each multi-level page having a type selected from the group consisting of a lower multi-level page, a middle multi-level page, an upper multi-level page, and a top multi-level page;
determine address information for the write data of the multi-level pages;
a packetizer comprising:
a header generator configured to:
generate a set of headers for flash management units, the flash management units comprising the write data of the multi-level pages; and
generate an extended header for flash management units configured to be stored on the lower multi-level page, the extended header comprising a digest comprising address information for write data configured to be stored on the middle multi-level page, the upper multi-level page; and the top multi-level page;
an ECC codeword generator configured to:
generate ECC codewords for the flash management units that comprise the write data of the middle mufti-level page, the upper multi-level page, and the top multi-level page;
generate lower page ECC codewords for the flash management units that comprise the write data of the lower multi-level page, wherein the lower page ECC codewords have a lower ECC strength than the ECC codewords for the flash management units that comprise the write data of the middle multi-level page, the upper multi-level page, and the top multi-level page; and
a read/write circuit configured to store the ECC codewords on the middle multi-level page, the upper multi-level page, and the top multi-level page and store the lower page ECC codewords on the lower multi-level page of a page of the non-volatile memory array.
18. The system of claim 17 , further comprising a header scanner configured to:
read a set of digests from the lower page ECC codewords; and
determine address information for the flash management units that comprise the write data of the middle multi-level page, the upper multi-level page, and the top multi-level page based on a single read of the lower multi-level page of the page of the non-volatile memory array.
19. The system of claim 17 , wherein each extended header for the flash management units configured to be stored on the lower multi-level page comprises address information for a flash management unit of the lower multi-level page and the digest comprises address information for at least one flash management unit from each of the middle multi-level page, the upper multi-level page, and the top multi-level page.