IP Library Granted Patent US 11,487,439
Granted Patent B1
US 11,487,439 · App. 17/331,958 · Granted Nov 1, 2022

Utilizing host memory buffers for storage device recoveries

Inventors: Kiran Kumar Eemani (Bangalore, IN); Sridhar Prudviraj Gunda (Bangalore, IN); Shivam Chawla (Bangalore, IN); Vikram Kumar (Bangalore, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/0619G06F3/0656G06F3/0679
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Quick Facts
Patent No.
US 11,487,439
App. No.
17/331,958
Granted
Nov 1, 2022
Kind
B1
Abstract

Storage devices include a memory array which stores host data received from a host computing device. During normal operations, the storage device may encounter a fatal error which can halt functionality. To restore functionality without system disconnection or third-party interventions, the storage device can store recovery data within a host memory buffer prior to encountering a fatal error. The recovery data can be replay protected memory data and/or firmware recovery data that can be written to the host memory buffer upon power on or during a firmware update. When a fatal error occurs, the recovery data can be accessed to try and rebuild file and mapping systems to restore full operation of the storage device. When full operational restoration is not possible, host data can at least be copied from the storage device prior to utilizing firmware recovery data to restore the storage device to an erased but functional state.

Claims (51)

1. A device comprising:

a processor;

a memory array comprising a plurality of memory devices; and

a storage device recovery logic configured to:

copy replay protected memory data to a secure host memory buffer;

detect a critical error occurring within the storage device;

execute a fatal error response process within the storage device;

load the replay protected memory data from the secure host memory buffer;

process the replay protected memory data;

attempt to write data to the memory array; and

operate the storage device based on the attempted data write.

2. The device of claim 1 , wherein in response to the attempted data write being successful, the storage device continues normal operation.

3. The device of claim 1 , wherein in response to the attempted data write failing, the storage device converts to a read-only mode.

4. The device of claim 3 , wherein the storage device recovery logic is further configured to perform a data recovery operation upon conversion to read-only mode.

5. The device of claim 1 , wherein processing the replay protected data includes access a previous copy of boot information.

6. The device of claim 5 , wherein, upon access of a previous copy of boot information, the storage device is rebooted.

7. The device of claim 6 , wherein, upon reboot, previously stored internal file system data is accessed by the previous copy of boot information.

8. The device of claim 7 , wherein a logical mapping table can be loaded by the previous copy of boot information.

9. The device of claim 1 , wherein the loading of the replay protected memory data occurs upon completion of the fatal error response process.

10. A device comprising:

a processor;

a memory array comprising a plurality of memory devices; and

a storage device recovery logic configured to:

generate firmware recovery data;

copy the generated firmware recovery data within a secure host memory buffer;

detect a critical error occurring within the storage device;

execute a fatal error response process within the storage device;

load firmware recovery data from the secure host memory buffer; and

execute a firmware recovery utilizing the firmware recovery data.

11. The device of claim 10 , wherein the generation of firmware occurs upon each update of the storage device firmware.

12. The device of claim 10 , wherein the storage device recovery logic is further configured to determine if a copy of firmware recover data is present within a host memory buffer prior to updating the storage device firmware.

13. The device of claim 10 , wherein upon determining that no firmware recovery data is stored within a host memory buffer, a request to allocate host memory buffer space is generated.

14. The device of claim 10 , wherein the storage device recovery logic is further configured to additionally copy the generated firmware recovery data within the memory array.

15. The device of claim 10 , wherein the storage device recovery logic is further configured to determine if the storage device health exceeds a predetermined threshold.

16. The device of claim 15 , wherein, in response to the storage device health not exceeding the predetermined threshold, the firmware recovery is not executed.

17. The device of claim 15 , wherein the execution of the firmware recovery occurs automatically in response to the storage device health exceeding the predetermined threshold.

18. A device comprising:

a processor;

a memory array comprising a plurality of memory devices; and

a storage device recovery logic configured to:

copy firmware recovery data and replay protected memory data to a host memory buffer;

detect a critical error occurring within the storage device;

execute a fatal error response process within the storage device;

load and process the replay protected memory data from the host memory buffer;

recover user data within the memory array;

load the firmware recovery data from the host memory buffer; and

execute a firmware recovery utilizing the firmware recovery data.

19. The device of claim 18 , wherein the storage device recovery logic is further configured to:

reboot the storage device; and

return the storage device to normal operations.

20. The device of claim 18 , wherein the storage device recovery logic is configured to operate automatically upon detection of a critical error occurring within the storage device.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 057651 FRAME 0296 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058981/0958 →
SECURITY INTEREST Recorded Sep 17, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 057651/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2021
From: EEMANI, KIRAN KUMAR; GUNDA, SRIDHAR PRUDVIRAJ; CHAWLA, SHIVAM; KUMAR, VIKRAM
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 056370/0565 →