IP Library Granted Patent US 9,135,106
Granted Patent B2
US 9,135,106 · App. 13/899,447 · Granted Sep 15, 2015

Read level adjustment using soft information

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Quick Facts
Patent No.
US 9,135,106
App. No.
13/899,447
Filed
May 21, 2013
Granted
Sep 15, 2015
Kind
B2
Art Unit
2117
USPC
714/773
Abstract

A method for calibrating read levels in a flash memory device is provided. The method includes receiving read information from flash memory in response to a read command, assigning soft information to the received read information, determining an error signal based on the assigned soft information, determining a read level offset based on the error signal, and adjusting a read level in the flash memory by the determined read level offset.

Claims (57)

1. A method for calibrating read levels in a flash memory device comprising:

receiving read information from flash memory for a plurality of cells in the flash memory in response to a read command;

assigning soft information comprising a log likelihood ratio to the received read information for each of the plurality of cells;

determining an error signal based on the assigned log likelihood ratios;

determining a read level offset based on the error signal; and

adjusting a read level in the flash memory by the determined read level offset.

2. The method of claim 1 , wherein determining the error signal comprises calculating an average log likelihood ratio for the plurality of cells in the flash memory.

3. The method of claim 1 , wherein determining the error signal comprises calculating an average sign for the log likelihood ratios of the plurality of cells in the flash memory.

4. The method of claim 1 , further comprising:

receiving read information from the flash memory for another plurality of cells in response to a plurality of read commands;

assigning soft information to the received read information for each of the other plurality of cells responsive to the plurality of read commands; and

accumulating the assigned soft information,

wherein the error signal is determined based on the accumulated soft information.

5. The method of claim 4 , further comprising:

determining a cycle count for the flash memory,

wherein the error signal is determined based on the accumulated soft information if the cycle count is greater than a threshold value.

6. The method of claim 4 , further comprising:

determining a retention time for data stored in the flash memory,

wherein the error signal is determined based on the accumulated soft information if the retention time is greater than a threshold time.

7. The method of claim 1 , wherein determining a read level offset comprises identifying the read level offset associated with the determined error signal in a look-up table.

8. A flash memory device comprising:

flash memory; and

a controller configured to:

send a read command to the flash memory;

receive read information from the flash memory for a plurality of cells in the flash memory in response to the read command;

assign soft information comprising a log likelihood ratio to the received read information for each of the plurality of cells;

determine an error signal based on the assigned log likelihood ratios;

determine a read level offset based on the error signal; and

adjust a read level in the flash memory by the determined read level offset.

9. The flash memory device of claim 8 ,

wherein the controller comprises a log likelihood generator configured to receive the read information from the flash memory for another plurality of cells and assign the soft information to the received read information for each of the other plurality of cells.

10. The flash memory device of claim 9 , wherein the controller is configured to determine the error signal by calculating an average log likelihood ratio for the plurality of cells in the flash memory.

11. The flash memory device of claim 9 , wherein the controller is configured to determine the error signal by calculating an average sign for the log likelihood ratios of the plurality of cells in the flash memory.

12. The flash memory device of claim 9 , wherein the controller is further configured to:

send a plurality of read commands to the flash memory;

receive read information for another plurality of cells in the flash memory in response to the plurality of read commands;

assign soft information to the received read information for each of the other plurality of cells responsive to the plurality of read commands;

accumulate the assigned soft information; and

determine the error signal based on the accumulated soft information.

13. The flash memory device of claim 12 , wherein the controller is further configured to determine a cycle count for the flash memory,

wherein the controller is configured to determine the error signal based on the accumulated soft information if the cycle count is greater than a threshold value.

14. The flash memory device of claim 12 , wherein the controller is further configured to determine a retention time for data stored in the flash memory,

wherein the controller is configured to determine the error signal based on the accumulated soft information if the retention time is greater than a threshold time.

15. The flash memory device of claim 8 , wherein the controller is configured to determine the read level offset by identifying the read level offset associated with the error signal in a look-up table.

16. A non-transitory machine-readable medium having instructions stored thereon which, when executed by a processor, cause the processor to perform operations for:

receiving read information for a plurality of cells in flash memory in response to a read command;

assigning a log likelihood ratio to the received read information for each of the plurality of cells in the flash memory;

determining an error signal based on the assigned log likelihood ratios;

determining a read level offset based on the error signal; and

adjusting a read level in the flash memory by the determined read level offset.

17. The non-transitory machine-readable medium of claim 16 , wherein determining the error signal comprises calculating an average log likelihood ratio for the plurality of cells in the flash memory.

18. The non-transitory machine-readable medium of claim 16 , wherein determining the error signal comprises calculating an average sign for the log likelihood ratios of the plurality of cells in the flash memory.

19. The non-transitory machine-readable medium of claim 16 , wherein the operations further comprise:

receiving read information for another plurality of cells in the flash memory in response to a plurality of read commands;

assigning soft information for each of the other plurality of cells in the flash memory responsive to the plurality of read commands; and

accumulating the assigned soft information,

wherein the error signal is determined based on the accumulated soft information.

Assignments (10)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2018
From: HGST TECHNOLOGIES SANTA ANA, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046174/0446 →