Optimization of an active range of mSets stored in a compressed address table
A controller maintains logical block address (LBA) to physical block address (PBA) mappings as mSets in a storage address table (SAT). Because the SAT may include many mappings, and, consequently, have a large size, the SAT may be stored in a distanced memory from the controller, such as a non-volatile memory device of the data storage device or a host memory buffer of a host device that is coupled to the data storage device. In order to optimize performance, a portion of the SAT may be stored as a compressed address table (CAT) in an internal memory of the controller or another volatile memory of the data storage device. During operation, the controller maintains an active range of mSets in the CAT by adding mSets to the CAT based on whether the LBA is sequential to the active range and a hit count of the active range.
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
determine that an address associated with a received read command is not stored in a compressed address table (CAT) of the data storage device, wherein the CAT comprises one or more ranges, wherein each of the one or more ranges corresponds with at least an mSet of a storage address table (SAT);
update either a lower bound or an upper bound of a range of the one or more ranges based on the address, wherein the range that is updated is closest to the address associated with the received read command;
retrieve one or more mSets from the SAT based on the updating, wherein the retrieved one or more mSets comprises the address associated with the received read command; and
store the retrieved one or more mSets in the CAT for subsequent address translation requests, wherein the controller is further configured to scan the CAT for the subsequent address translation requests.
2. The data storage device of claim 1 , wherein the SAT is stored in a non-volatile memory device of the data storage device.
3. The data storage device of claim 1 , wherein the SAT is stored in a host memory buffer (HMB) of a host device.
4. The data storage device of claim 1 , wherein a first portion of the SAT is stored in a non-volatile memory device of the data storage device and a second portion of the SAT is stored in a host memory buffer (HMB) of a host device.
5. The data storage device of claim 1 , wherein the one or more ranges are reset after a predetermined number of address translation requests have been serviced.
6. The data storage device of claim 1 , wherein the controller is further configured to merge overlapping ranges of the one or more ranges.
7. The data storage device of claim 1 , wherein the CAT is stored in volatile memory of the data storage device.
8. The data storage device of claim 1 , wherein the data storage device is dynamic random access memory (DRAM)-less.
9. The data storage device of claim 1 , wherein the updating occurs when the address associated with the read command is sequential to the range of the one or more ranges based on the address.
10. A data storage device, comprising:
a non-volatile memory device;
a volatile memory device, wherein:
the volatile memory device comprises a compressed address table (CAT), wherein the CAT stores a portion of a storage address table (SAT), wherein the SAT stores logical block address (LBA) to physical block address (PBA) mappings, and wherein the CAT stores one or more ranges of LBA to PBA mappings; and
a controller coupled to the non-volatile memory device and the volatile memory device, wherein the controller is configured to:
determine that an address associated with a read command is not stored in the CAT;
determine if the address associated with the read command is sequential to one of the one or more ranges of LBA to PBA mappings of the CAT when the address associated with the read command is not stored in the CAT; and
retrieve and store an mSet storing an LBA to PBA mapping corresponding to the address associated with the read command in the CAT when the address associated with the read command is sequential to one of the one or more ranges of LBA to PBA mappings of the CAT.
11. The data storage device of claim 10 , wherein the portion is a copy of data stored in the SAT.
12. The data storage device of claim 10 , wherein the volatile memory device is disposed in the controller.
13. The data storage device of claim 10 , wherein the volatile memory further comprises a temporary CAT.
14. The data storage device of claim 13 , wherein the controller is further configured to retrieve and store the mSet storing the LBA to PBA mapping corresponding to the address associated with the read command in the temporary CAT when the address associated with the read command is not sequential to one of the one or more ranges of LBA to PBA mappings of the CAT.
15. The data storage device of claim 14 , wherein the controller is further configured to:
receive another read command corresponding to the mSet stored in the temporary CAT; and
copy the mSet stored in the temporary CAT to the CAT.
16. The data storage device of claim 10 , wherein the controller is further configured to maintain an access count of each of the one or more ranges.
17. The data storage device of claim 16 , wherein the controller is further configured to reset a range of the one or more ranges after a number of read commands have been processed, wherein the range that is reset is determined by the access count.
18. The data storage device of claim 10 , wherein the one or more ranges is two or more ranges, wherein the controller is further configured to:
determine that a first range of the two or more ranges and a second range of the two or more ranges are consecutive or overlapping; and
merge the first range and the second range.
19. A data storage device, comprising:
means for storing data; and
a controller coupled to the means for storing data, wherein the controller is configured to:
adjust a stored range of mSets in a compressed address table (CAT) based on determining that an mSet comprising an address associated with a read command is sequential to the stored range.
20. The data storage device of claim 19 , wherein the mSet is retrieved from a storage address table (SAT) stored in the means for storing data or a host memory buffer (HMB) of a host device.