Non-volatile memory die with deep learning neural network
Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.
1. An apparatus, comprising:
a die comprising non-volatile memory (NVM) elements;
a plurality of neural network processing circuits formed in the die and configured to read synaptic weight values in parallel from a plurality of word lines of NVM elements of the die and perform neural network operations in parallel using the synaptic weight values; and
a circuit formed on the die and configured to perform an on-chip NVM fold operation to:
read at least some of the synaptic weight values from a plurality of first word lines of the plurality of word lines, each of the first word lines comprising single-level-cell (SLC) NVM elements of a portion of the NVM configured to operate in an SLC mode,
update the synaptic weight values read from the first word lines using at least one of the plurality of the neural network processing circuits, and
store the updated synaptic weight values in a second word line of the plurality of word lines, the second word line comprising multi-level-cell (MLC) NVM elements of a portion of the NVM configured to operate in an MLC mode.
2. A method, comprising:
storing synaptic weight values for a neural network within a plurality of word lines of non-volatile memory (NVM) elements of a die;
reading a plurality of the synaptic weight values in parallel from the word lines of the NVM elements;
performing neural network operations in parallel using the synaptic weight values, wherein the neural network operations are performed in parallel by a plurality of neural network processing components formed within the die; and
wherein at least one of the neural network operations comprises performing an on-chip NVM fold operation by:
reading at least some of the synaptic weight values from a plurality of first word lines of the plurality of word lines, each of the first word lines comprising single-level-cell (SLC) NVM elements of a portion of the NVM configured to operate in an SLC mode,
updating the synaptic weight values read from the first word lines using at least one of the plurality of the neural network processing components, and
storing the updated synaptic weight values in a second word line of the plurality of word lines, the second word line comprising multi-level-cell (MLC) NVM elements of a portion of the NVM configured to operate in an MLC mode.
3. The method of claim 2 , further comprising:
performing neural network operations in parallel using the synaptic weight values, wherein the neural network operations are performed in parallel by a plurality of neural network processing components formed within the die, the plurality of neural network processing components comprising multiplexers (MUXes) and multiply-accumulate (MAC) components, with the MUXes configured to route particular synaptic weight values to particular MAC circuits in accordance with a particular MUX connectivity configuration;
modifying the MUX connectivity configuration for a different layer of a neural network and then performing additional neural network operations; and
wherein each neural network layer is stored in a separate NAND block of the die.
4. The apparatus of claim 1 , further comprising:
a plurality of neural network processing circuits formed in the die and configured to access synaptic weight values in parallel from the word lines of a NAND block of the die and perform neural network operations in parallel using the synaptic weight values, the plurality of neural network processing circuits comprising multiplexers (MUXes) and multiply-accumulate (MAC) circuits, with the MUXes configured to route particular synaptic weight values to particular MAC circuits in accordance with a particular MUX connectivity configuration;
a MUX connectivity configuration circuit formed in the die and configured to determine the particular MUX connectivity configuration for different layers of a neural network; and
wherein each neural network layer is stored in a separate NAND block of the die.