IP Library Granted Patent US 11,294,819
Granted Patent B2
US 11,294,819 · App. 16/835,836 · Granted Apr 5, 2022

Command optimization through intelligent threshold detection

Inventors: Robert Ellis (Phoenix, AZ); Kevin O'Toole (Chandler, AZ); Jacob Schmier (Gilbert, AZ); Todd Lindberg (Phoenix, AZ); Atif Hussain (Longmont, CO); Venugopal Garuda (Denver, CO)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F12/0882G06F9/30029G06F12/0246G06F13/1668G11C16/26G11C16/30
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Quick Facts
Patent No.
US 11,294,819
App. No.
16/835,836
Granted
Apr 5, 2022
Kind
B2
Abstract

Aspects of a storage device including a memory and a controller are provided which prevent retransmissions of set features commands with identical read voltage threshold offsets for the same die. When the controller receives a first read command for data stored in the memory, the controller identifies a first parameter to modify a first read threshold, and executes a first set features command for modifying the read threshold based on the first parameter. Subsequently, when the controller receives a second read command from the host device for data stored in the memory, the controller identifies a second parameter to modify a second read threshold, and determines whether the first and second parameters are the same. If the parameters are the same, the controller refrains from executing a second set features command for modifying the second read threshold. Thus, the read latency of the storage device may be reduced.

Claims (34)

1. A storage device, comprising:

a memory including a first memory location and a second memory location; and

a controller configured to receive a first read command from a host device for data stored in the first memory location, to identify a first parameter to modify a first read threshold associated with the first memory location, and to execute a first set features command for modifying the first read threshold based on the first parameter;

wherein the controller is further configured to receive a second read command from the host device for data stored in the second memory location, to identify a second parameter to modify a second read threshold associated with the second memory location, and to refrain from executing a second set features command for modifying the second read threshold when the second parameter is the same as the first parameter.

2. The storage device of claim 1 , wherein the first parameter comprises a first voltage setting, and the second parameter comprises a second voltage setting.

3. The storage device of claim 1 , wherein the memory further comprises cache, and wherein the controller is further configured to store the first parameter in the cache.

4. The storage device of claim 1 , wherein the controller is further configured to determine when the second parameter is the same as the first parameter using a comparator.

5. The storage device of claim 4 , wherein the comparator comprises one or more exclusive-or (XOR) gates or exclusive-nor (XNOR) gates.

6. The storage device of claim 1 , wherein the memory includes a die having the first memory location and the second memory location, and wherein the first parameter and the second parameter each indicate the die.

7. The storage device of claim 1 , wherein the first memory location includes a first page, wherein the second memory location includes a second page, and wherein the first parameter indicates the first page and the second parameter indicates the second page.

8. A method, comprising:

receiving a first read command from a host device for data stored in a first memory location of a memory of a storage device;

identifying a first parameter to modify a first read threshold associated with the first memory location;

executing a first set features command for modifying the first read threshold based on the first parameter;

receiving a second read command from the host device for data stored in a second memory location of the memory of the storage device;

identifying a second parameter to modify a second read threshold associated with the second memory location; and

refraining from executing a second set features command for modifying the second read threshold when the second parameter is the same as the first parameter.

9. The method of claim 8 , wherein the first parameter comprises a first voltage setting, and wherein the second parameter comprises a second voltage setting.

10. The method of claim 8 , further comprising:

determining when the second parameter is the same as the first parameter using a comparator.

11. The method of claim 10 , wherein the comparator comprises one or more exclusive-or (XOR) gates or exclusive-nor (XNOR) gates.

12. The method of claim 8 , wherein the memory includes a die having the first memory location and the second memory location, and wherein the first parameter and the second parameter each indicate the die.

13. The method of claim 8 , wherein the first memory location includes a first page and the second memory location includes a second page, and wherein the first parameter indicates the first page and the second parameter indicates the second page.

14. A storage device, comprising:

a memory including a first memory location and a second memory location;

a controller configured to receive a first read command from a host device for data stored in the first memory location, to identify a first parameter to modify a first read threshold associated with the first memory location, to execute a first set features command for modifying the first read threshold based on the first parameter, to receive a second read command from the host device for data stored in the second memory location, and to identify a second parameter to modify a second read threshold associated with the second memory location; and

means for comparing the first parameter with the second parameter;

wherein the controller is further configured to determine when the second parameter is the same as the first parameter based on the means for comparing, and to refrain from executing a second set features command for modifying the second read threshold when the second parameter is the same as the first parameter.

15. The storage device of claim 14 , wherein the first parameter comprises a first voltage setting, and the second parameter comprises a second voltage setting.

16. The storage device of claim 14 , wherein the memory further comprises cache, and wherein the controller is further configured to store the first parameter in the cache.

17. The storage device of claim 14 , wherein the means for comparing comprises one or more exclusive-or (XOR) gates.

18. The storage device of claim 14 , wherein the means for comparing comprises one or more exclusive-nor (XNOR) gates.

19. The storage device of claim 14 , wherein the memory includes a die having the first memory location and the second memory location, and wherein the first parameter and the second parameter each indicate the die.

20. The storage device of claim 14 , wherein the first memory location includes a first page, wherein the second memory location includes a second page, and wherein the first parameter indicates the first page and the second parameter indicates the second page.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2020
From: ELLIS, ROBERT; O'TOOLE, KEVIN; SCHMIER, JACOB; LINDBERG, TODD; HUSSAIN, ATIF; GARUDA, VENUGOPAL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052450/0684 →