Method and system for improving word line data retention for memory blocks
Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.
1. A method for managing a block in a storage device, comprising:
accessing a failed bit count (FBC) for a word line in the block, wherein the block has one or more programmed word lines in a programmed region, and one or more unprogrammed word lines in an unprogrammed region, and wherein the word line separates the programmed word lines of the programmed region from the unprogrammed word lines of the unprogrammed region;
determining whether the FBC of the word line exceeds a predetermined threshold;
in response to the FBC of the word line exceeding the predetermined threshold, performing pre-verify operations on one or more of the programmed word lines in the programmed region;
programming the word line with first data equal to second data that is programmed in a second block in the storage device; and
in response to preventing further pre-verify operations on the respective programmed word lines, programming the unprogrammed word lines in the unprogrammed region of the block.
2. The method of claim 1 , wherein the programmed first data of the word line is configured by a soft program component.
3. The method of claim 2 , wherein the soft program component is configured to reduce the accessed FBC of the word line to a second FBC for the word line that does not exceed the predetermined threshold, and wherein the second FBC of the word line is substantially less than the accessed FBC of the word line.
4. The method of claim 3 , wherein the block comprises an open block until all word lines in the block are programmed, wherein the word line is a boundary word line, and the boundary word line is the last programmed word line among the programmed word lines in the programmed region.
5. The method of claim 1 , wherein the second block comprises a source block, and wherein the source block comprises at least one or more of a source single-level cell (SLC) block, a multi-level cell (MLC) block, a triple-level cell (TLC) block, a qual-level cell (QLC) block, a penta-level cell (PLC) block, and any other predetermined block.
6. The method of claim 4 , wherein the soft program component comprises a soft-fine programming operation and a soft programming operation.
7. The method of claim 6 , wherein the soft-fine programming operation is performed on the boundary word line when the block comprises a first block type, and wherein the first block type comprises at least one or more of a SLC block, a MLC block, a TLC block, a QLC block, a PLC block, and any other particular type of memory cell block.
8. The method of claim 6 , wherein the soft programming operation is performed on the boundary word line when the block comprises a second block type, and wherein the second block type comprises at least one or more of a SLC block, a MLC block, a TLC block, a QLC block, a PLC block, and any other particular type of memory cell block.
9. The method of claim 1 , further comprising:
in response to the FBC of the word line not exceeding the predetermined threshold, programming the unprogrammed word lines in the unprogrammed region of the block without both performing the pre-verify operations and programming the word line with the first data.
10. The method of claim 6 , wherein the FBC is accessed for each page of the word line in the block, and wherein the soft program component includes one or more tunable parameters that are configured to control both the soft and soft-fine programming operations.
11. The method of claim 10 , wherein the one or more tunable parameters comprise a delta of program voltages and a predetermined number of pre-verify operations.
12. A storage device, comprising:
one or more memories; and
one or more controllers configured to:
access one or more failed bit counts (FBCs) for one or more pages of a word line in a block, wherein the block has one or more programmed word ones in a programmed region, and one or more unprogrammed word lines in an unprogrammed region, and wherein the word line separates the programmed word lines of the programmed region from the unprogrammed word lines of the unprogrammed region;
determine whether any of the FBCs of any of the pages of the word line exceed a predetermined threshold;
in response to all FBCs of all pages of the word line exceeding the predetermined threshold, perform pre-verify operations on one or more of the programmed word lines in the programmed region;
programming the word line with first data equal to second data that is programmed in a second block in the storage device, wherein the programmed first data of the word line is configured by a soft program component, wherein the soft program component is configured to reduce all accessed FBCs of the word line to second FBCs or the word line that does not exceed the predetermined threshold, and wherein the second FBCs of the word line are substantially less than all accessed FBCs of the word line; and
in response to preventing further pre-verify operations on the respective programmed word lines, programming the unprogrammed word lines in the unprogrammed region of the block.
13. The storage device of claim 12 , wherein the block comprises an open block until all word lines in the block are programmed, wherein the word line is a boundary word line, and wherein the boundary word line is the last programmed word line from the programmed word lines in the programmed region.
14. The storage device of claim 12 , wherein the second block comprises a source block, and wherein the source block comprises at least one or more of a SLC block, a MLC block, a TLC block, a QLC block, a PLC block, and any other predetermined block.
15. The storage device of claim 12 , wherein the soft program component comprises a soft-fine programming operation and a soft programming operation, and wherein the soft program component includes one or more tunable parameters that are configured to control both the soft and soft-fine programming operations.
16. The storage device of claim 15 , wherein the soft-fine programming operation is performed on the boundary word line when the block comprises a first block type, and wherein the first block type comprises at least one or more of a SLC block, a MLC block, a TLC block, a QLC block, a PLC block, and any other particular type of memory cell blocks.
17. The storage device of claim 15 , wherein the soft programming operation is performed on the boundary word line when the block comprises a second block type, and wherein the second block type comprises at least one or more of a SLC block, a MLC block, a TLC block, a QLC block, a PLC block, and any other particular type of memory cell blocks.
18. The storage device of claim 12 , wherein:
in response to the FBCs of the pages of the word line not exceeding the predetermined threshold, programming the unprogrammed word lines in the unprogrammed region of the block without both performing the pre-verify operations and programming the word line with the first data.
19. The storage device of claim 15 , wherein the one or more tunable parameters comprise a delta of program voltages and a predetermined number of pre-verify operations.
20. A storage device, comprising:
a failed bit count (FBC) reduction device;
one or more memories communicatively coupled to the FBC reduction device; and
one or more controllers communicatively coupled to at least one or more of the memories and the FBC reduction device, wherein the FBC reduction device comprises:
a FBC count component configured to access a FBC for a word line in a block, wherein the block has one or more programmed word lines in a programmed region, and one or more unprogrammed word lines in an unprogrammed region, and wherein the word line separates the programmed word lines of the programmed region from the unprogrammed word lines of the unprogrammed region;
a threshold component configured to determine whether the FBC of the word line exceeds a predetermined threshold;
a pre-verify component configured to, in response to the FBC of the word line exceeding the predetermined threshold, perform pre-verify operations on one or more of the programmed word lines in the programmed region; a soft program component configured to program the word line with first data equal to second data that is programmed in a second block in the storage device; and
a program component configured to, in response to preventing further pre-verify operations on the respective programmed word lines, program the unprogrammed word lines in the unprogrammed region of the block.