IP Library Granted Patent US 9,304,709
Granted Patent B2
US 9,304,709 · App. 14/020,653 · Granted Apr 5, 2016

High performance system providing selective merging of dataframe segments in hardware

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Quick Facts
Patent No.
US 9,304,709
App. No.
14/020,653
Granted
Apr 5, 2016
Kind
B2
Abstract

A method of writing data to a range of logical blocks in a storage medium includes: receiving a command including a starting logical block address, a value indicating a range of logical block addresses to be written, and a logical block of data; storing the logical block in a first temporary storage; generating a logical page by duplicating the logical block a plurality of times corresponding to a number of logical blocks in a logical page and transporting the generated logical page to a second temporary storage and storing the generated logical page in the second temporary storage; writing the generated logical page from the second temporary storage into the storage medium beginning from the starting logical block address; and performing a read-modify-write operation if the first write operation does not begin on a logical page boundary or the last write operation does not end on a logical page boundary.

Claims (32)

1. A method of writing data to a range of logical blocks in a storage medium, the method comprising:

receiving a command comprising a starting logical block address, a value indicating a range of logical block addresses to be written, and a logical block of data;

storing the logical block of data in a first temporary storage;

generating a logical page by duplicating the logical block of data a plurality of times corresponding to a number of logical blocks comprising a logical page and transporting the generated logical page to a second temporary storage and storing the generated logical page in the second temporary storage;

writing the generated logical page from the second temporary storage into the storage medium beginning from the starting logical block address, wherein the writing the generated logical page is performed as a background task to other write operations involving merging; and

performing a read-modify-write operation if the first write operation does not begin on a logical page boundary or the last write operation does not end on a logical page boundary.

2. The method of claim 1 , wherein the second temporary storage is a queue in a read-modify-write module.

3. The method of claim 2 , further comprising reserving the queue in a read-modify-write module prior to transporting and storing the generated logical page in the queue.

4. The method of claim 1 , further comprising:

updating a count based on a number of logical blocks in the range of logical block addresses written to the storage medium in a current logical page and comparing the count to the value indicating the range of logical block addresses; and

if the count matches the value indicating the range of logical block addresses, generating a signal indicating the writing is complete.

5. The method of claim 1 , wherein each logical page comprises a predetermined number of logical blocks.

6. The method of claim 5 , wherein each logical block comprises one of about 512 bytes of data, about 1024 bytes of data, about 2048 bytes of data, and about 4096 bytes of data.

7. The method of claim 6 , wherein the data bytes comprise all ones or all zeros.

8. The method of claim 6 , wherein the data bytes comprise predetermined data.

9. The method of claim 6 , wherein each logical block further comprises additional bytes of metadata.

10. The method of claim 9 , wherein the metadata for each logical block is updated with the logical block address into which the logical block is to be written.

11. The method of claim 1 , wherein the value indicating the range of logical block addresses is a value indicating all of the logical block address of the storage medium.

12. The method of claim 1 , wherein the generating a logical page is performed by a processor.

13. An apparatus for writing data to a range of logical blocks, the apparatus comprising:

a first device configured to receive a command comprising a starting logical block address, a value indicating a range of logical block addresses, and a logical block of data;

a first temporary storage configured to store the logical block of data;

a processor configured to generate a logical page by duplicating the logical block of data a plurality of times corresponding to a number of logical blocks comprising a logical page, and transport the generated logical page to a second temporary storage;

a storage medium configured to store logical pages;

write circuitry configured to write the generated logical page from the second temporary storage into the storage medium beginning from the starting logical block address, wherein the write circuitry writes the logical page from the second temporary storage into the storage medium as a background task to other write operations involving merging; and

a read-modify-write module configured to perform a read-modify-write operation if the first write operation does not begin on a logical page boundary or the last write operation does not end on a logical page boundary.

14. The apparatus of claim 13 , wherein the second temporary storage is a queue in the read-modify-write module.

15. The apparatus of claim 14 , further comprising reserving the queue in the read-modify-write module prior to transporting and storing the generated logical page in the queue.

16. The apparatus of claim 13 , further comprising a counter configured to count a number of logical blocks in the range of logical block addresses written to the storage medium in a current logical page and compare the count to the value indicating the range of logical block addresses.

17. The apparatus of claim 16 , further comprising circuitry configured to generate an indication signal when the comparison indicates that the value indicating the range of logical block addresses is reached.

18. The apparatus of claim 13 , further comprising a read-modify-write module comprising circuitry configured to generate a cyclic redundancy code (CRC) for the generated logical page by accumulating CRC data of the logical blocks written into the output logical page on a block-by-block basis.

19. The apparatus of claim 18 , wherein the read-modify-write module is further configured to calculate a data integrity field for each block and insert the calculated data integrity field between the blocks.

Assignments (13)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2018
From: SKYERA, LLC
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046726/0328 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →