IP Library Granted Patent US 11,537,534
Granted Patent B2
US 11,537,534 · App. 17/181,907 · Granted Dec 27, 2022

High throughput, low power, high parity architecture for database SSD

Inventors: Israel Zimmerman (Ashdod, IL); Mahmud Asfur (Bat-Yam, IL); Mordekhay Zehavi (Raanana, IL)
Assignee: Western Digital Technologies, Inc.
G06F13/161G06F11/1004G06F13/1668G06F15/80G06F16/2379H03M13/1102
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Quick Facts
Patent No.
US 11,537,534
App. No.
17/181,907
Granted
Dec 27, 2022
Kind
B2
Abstract

A method and apparatus for the increase of internal data throughput and processing capability for SSD's, to enable processing of database commands on an SSD. A front-end ASIC is provided with 256 to 512 RISC processing cores to enable decomposition and parallelization of host commands to front-end module (FM) ASICs that each in turn are coupled to multiple NVM dies, as well as processing of host database operations such as insert, select, update, and delete. Each FM ASIC is architected to increase parity bits to 33.3% of NVM data, and process parity data with 14 LDPC's. By increasing the parity bits to 33.3%, BER is reduced, power consumption is reduced, and data throughput within the SSD is increased.

Claims (27)

1. A data storage device, comprising:

a front-end module (FM) application-specific integrated circuit (ASIC) (FM ASIC) comprising a plurality of low density parity-check (LDPC) engines, and a plurality of flash interface modules (FIMs), each FIM coupled to a respective one of a plurality of non-volatile memory (NVM) dies capable of storing data; and

a front-end ASIC (FE ASIC) comprising a plurality of processing cores and coupled to the FM ASIC, configured to receive a database instruction from a host comprising one of a select, an update, an insert, and a delete instruction, and executing the database instruction with the plurality of processing cores within the data storage device.

2. The data storage device of claim 1 , wherein more than 10.0% of the data stored on one of the plurality of NVM dies is parity data.

3. The data storage device of claim 2 , wherein 33.3% of the data stored on one of the plurality of NVM dies is parity data.

4. The data storage device of claim 3 , wherein at least one of the plurality of NVM dies is a bit cost scalable (BiCS) 6 die.

5. The data storage device of claim 2 , wherein the number of LDPC engines is less than about 54.

6. The data storage device of claim 5 , wherein the number of LDPC engines is less than or equal to 14 LDPC engines.

7. The data storage device of claim 1 , wherein the number of processing cores is greater than 5 processing cores.

8. The data storage device of claim 7 , wherein the number of processing cores is between 256 processing cores and 512 processing cores.

9. A solid state storage device, comprising:

a front-end (FE) application-specific integrated circuit (ASIC) (FE ASIC) configured to be coupled to a host; and

a front-end module ASIC (FM ASIC) coupled to one or more non-volatile memory (NVM) dies, and having a bit error rate (BER) of 0.2 or less, the FM ASIC coupled to the FE ASIC.

10. The solid state storage device of claim 9 , configured to carry out database commands from a host upon data stored in the one or more NVM dies, comprising one of a select, an insert, an update, and a delete instruction.

11. The solid state storage device of claim 9 , wherein one of the one or more NVM dies comprises planes, wherein one of the planes of the one NVM die comprises parity data.

12. The solid state storage device of claim 11 , wherein 33.3% of data on the one NVM die comprises the parity data.

13. The solid state storage device of claim 12 , wherein the FM ASIC comprises fewer than 54 low-density parity-check (LDPC) engines.

14. The solid state storage device of claim 13 , wherein the FM ASIC comprises 14 LDPC engines.

15. The solid state storage device of claim 11 , wherein the one NVM die comprises a bit cost scalable (BiCS) 6 NVM die.

16. The solid state storage device of claim 9 , wherein the FE ASIC comprises between 256 processing cores to 512 processing cores, inclusive.

17. A device for storing data, comprising:

one or more memory means configured to store data;

a front-end module (FM) application-specific integrated circuit (ASIC) (FM ASIC) means coupled to the one or more memory means, the FM ASIC means configured to have a bit error rate (BER) of less than 0.2; and

a front-end ASIC (FE ASIC) means coupled to the FM ASIC means, configured to carry out database commands from a host, the database commands comprising one of a select, an insert, an update, and a delete.

18. The device for storing data of claim 17 , configured to cause 33.3% of the stored data to be parity data.

19. The device for storing data of claim 18 , wherein the FM ASIC means comprises 8 low-density parity-check (LDPC) engine means.

20. The device for storing data of claim 17 , wherein the FE ASIC comprises 256-512 processing means for carrying out the database commands.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2021
From: ZIMMERMAN, ISRAEL; ASFUR, MAHMUD; ZEHAVI, MORDEKHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055365/0301 →
Continuity (2)
Provisional Application 63068331 · Aug 20, 2020
Related Publication 20220058140A1 · Feb 24, 2022