Apparatus and methods for programming memory cells
An apparatus is provided that includes a memory die having a first memory cell, and a controller connected to the memory die. The controller is configured to apply a plurality of programming pulses to the first memory cell, apply a plurality of first verify pulses to the first memory cell, determine from the first verify pulses that the first memory cell has been programmed to a first programmed memory state, apply a single second verify pulse to the first memory cell after determining that the first memory cell has been programmed to the first programmed memory state, determine from the single second verify pulse that the first memory cell is no longer programmed to the first programmed memory state, and apply an additional programming pulse to the first memory cell.
1. An apparatus comprising:
a memory die comprising a first memory cell; and
a controller connected to the memory die, the controller configured to:
apply a plurality of programming pulses to the first memory cell;
apply a plurality of first verify pulses to the first memory cell;
determine from the first verify pulses that the first memory cell has been programmed to a first programmed memory state;
apply a single second verify pulse to the first memory cell after determining that the first memory cell has been programmed to the first programmed memory state;
determine from the single second verify pulse that the first memory cell is no longer programmed to the first programmed memory state; and
apply an additional programming pulse to the first memory cell.
2. The apparatus of claim 1 , wherein the controller is configured to apply the plurality of programming pulses and the plurality of first verify pulses in a sequence of program loops.
3. The apparatus of claim 1 , wherein the first memory cell is coupled to a bit line, and the controller is configured to bias the bit line to a first bias voltage while applying the plurality of programming pulses to the first memory cell, and bias the bit line to a second bias voltage greater than the first bias voltage while applying the additional programming pulse to the first memory cell.
4. The apparatus of claim 1 , wherein the controller is further configured to partially inhibit the first memory cell from being programmed while applying the additional programming pulse to the first memory cell.
5. The apparatus of claim 1 , wherein the controller is further configured to:
determine in a first program loop N that the first memory cell has been programmed to the first programmed memory state;
apply the single second verify pulse to the first memory cell in a second program loop N+i, where i≥1; and
apply the additional programming pulse to the first memory cell in a third program loop N+i+j, j≥1.
6. The apparatus of claim 1 , wherein:
the memory die further comprises a second memory cell; and
the controller is further configured to apply a third verify pulse to the second memory cell and then apply the single second verify pulse to the first memory cell.
7. The apparatus of claim 1 , wherein:
the memory die further comprises a second memory cell; and
the controller is further configured to apply a program pulse to the second memory cell while applying the additional program pulse to the first memory cell.
8. The apparatus of claim 1 , wherein:
the memory die further comprises a second memory cell;
the first memory cell is coupled to a first bit line;
the second memory cell is coupled to a second bit line; and
the controller is configured to:
bias the first bit line to a first bias voltage while applying the plurality of programming pulses to the first memory cell; and
bias the second bit line to the first bias voltage and bias the first bit line to a second bias voltage greater than the first bias voltage while applying the additional programming pulse to the first memory cell.
9. The apparatus of claim 1 , wherein:
the memory die further comprises a second memory cell; and
the controller is further configured to apply the plurality of programming pulses to the first memory cell to program the first memory cell to the first programmed memory state, and apply the plurality of programming pulses to the second memory cell to program the second memory cell to a second programmed memory state different from the first programmed memory state.
10. The apparatus of claim 1 , wherein:
the apparatus further comprises a plurality of data latches associated with the first memory cell; and
the controller is further configured to:
load the plurality of data latches with a code representing the first programmed memory state of the first memory cell prior to applying the plurality of programming pulses to the first memory cell; and
not reset the code loaded into the plurality of data latches after determining that the first memory cell has been programmed to the first programmed memory state.
11. The apparatus of claim 1 , wherein:
the apparatus further comprises a plurality of data latches associated with the first memory cell; and
the controller is further configured to:
load the plurality of data latches with a code representing the first programmed memory state of the first memory cell prior to applying the plurality of programming pulses to the first memory cell; and
maintain the code loaded into the plurality of data latches throughout an entire programming operation of the first memory cell.
12. A method comprising:
programming a first memory cell by applying a plurality of programming pulses and a plurality of first verify pulses to the first memory cell;
after applying each first verify pulse, determining if a threshold voltage of the first memory cell exceeds a first verify voltage level;
after determining that the threshold voltage of the first memory cell exceeds the first verify voltage level, applying a single second verify pulse to the first memory cell;
determining from the single second verify pulse that the threshold voltage of the first memory cell does not exceed the first verify voltage level; and
applying an additional programming pulse to the first memory cell to shift the threshold voltage of the first memory cell above the first verify voltage level.
13. The method of claim 12 , wherein the first memory cell is coupled to a bit line, and the method further comprises biasing the bit line to a first bias voltage while applying the plurality of programming pulses to the first memory cell, and biasing the bit line to a second bias voltage greater than the first bias voltage while applying the additional programming pulse to the first memory cell.
14. The method of claim 12 , further comprising applying the plurality of programming pulses and the plurality of first verify pulses in a sequence of program loops.
15. The method of claim 14 , further comprising:
determining in a first program loop N that the threshold voltage of the first memory cell is above the first verify voltage level;
applying the single second verify pulse to the first memory cell in a second program loop N+i, where i≥1; and
applying the additional programming pulse to the first memory cell in a third program loop N+i+j, j≥1.
16. The method of claim 12 , further comprising:
programming a second memory cell by applying the plurality of programming pulses to the second memory cell;
applying a third verify pulse to the second memory cell to determine if a threshold voltage of the second memory cell exceeds a second verify voltage level; and
applying the single second verify pulse to the first memory cell after applying the third verify pulse to the second memory cell.
17. The method of claim 12 , further comprising applying one of the plurality of programming pulses to the second memory cell while applying the additional program pulse to the first memory cell.
18. The method of claim 12 , wherein:
the first memory cell is associated with a plurality of data latches; and
the method further comprises:
loading the plurality of data latches with a code representing a first programmed memory state of the first memory cell prior to applying the plurality of programming pulses to the first memory cell; and
maintaining the code loaded into the plurality of data latches after determining that the threshold voltage of the first memory cell exceeds the first verify voltage level.
19. A system comprising:
a memory die comprising a memory cell and a plurality of data latches associated with the memory cell, the data latches loaded with a code representing a particular programmed memory state of the memory cell; and
a controller connected to the memory die, the controller configured to:
apply a plurality of programming pulses to the memory cell to program the memory cell to the particular memory state;
determine that the memory cell has been programmed to the particular programmed memory state;
after determining that the memory cell has been programmed to the particular programmed memory state, determine that a threshold voltage of the memory cell has shifted below a verify voltage level;
apply an additional programming pulse to the memory cell to shift the threshold voltage of the memory cell above the verify voltage level; and
maintain the code loaded into the plurality of data latches after determining that the memory cell has been programmed to the particular programmed memory state.
20. The system of claim 19 , wherein the memory cell is coupled to a bit line, and the controller is further configured to bias the bit line to a first bias voltage while applying the plurality of programming pulses to the memory cell, and bias the bit line to a second bias voltage greater than the first bias voltage while applying the additional programming pulse to the memory cell.