IP Library Granted Patent US 11,087,195
Granted Patent B2
US 11,087,195 · App. 16/375,529 · Granted Aug 10, 2021

Memory card pad layout supporting multiple communication protocols

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Quick Facts
Patent No.
US 11,087,195
App. No.
16/375,529
Granted
Aug 10, 2021
Kind
B2
Abstract

Memory cards having a nano card form factor configured according to different card standards. The nano card have a pair of opposed surfaces having a length and width of a nano SIM card in which a first group of interface pads on one of the opposed surfaces configured to mate with contact pins of a host device card slot operating per a PCIe memory card standard and a second group of interface pads configured to mate with contact pins of a host device card slot operating per a second memory card standard different than the PCIe memory card standard. The nano cards have patterns of pads allowing for vertical and horizontal insertion to a host device card slot being backward compatible with legacy host device card slots.

Claims (40)

1. A memory card, comprising:

a first group of interface pads configured to mate with contact pins of a host device card slot operating per a PCI Express (PCIe) memory card standard; and

a second group of interface pads configured to mate with contact pins of a host device card slot operating per a second memory card standard different than the PCIe memory card standard;

wherein an interface pad of at least one of the first group and the second group has a non-rectangular shape, comprising a first portion and a second portion at a right angle to the first portion;

wherein the first portion is configured to be contacted by a contact pin operating per one of the PCIe memory card standard and the second memory card standard upon horizontal insertion of the memory card in a first host device card slot; and

wherein the second portion is configured to be contacted by a contact pin operating per the same one of the PCIe memory card standard and the second memory card standard upon vertical insertion of the memory card in a second host device card slot.

2. The memory card of claim 1 , wherein the memory card has a nano card form factor.

3. The memory card of claim 2 , wherein the second memory card standard is an SD memory card standard.

4. The memory card of claim 2 , wherein the second memory card standard is a SIM memory card standard.

5. The memory card of claim 2 , wherein the second memory card standard is a Multimedia Card memory card standard.

6. The memory card of claim 1 , wherein the first and second groups of interface pads are provided on opposed sides of the memory card.

7. A memory card, comprising:

a pair of opposed surfaces having a length and width of a nano SIM card; and

interface pads on at least one of the opposed surfaces, at least one pad of the interface pads comprising:

a first portion, and

a second portion at a right angle to the first portion, the first portion joining to the second portion at a position between first and second ends of the first portion, the first portion configured to be contacted by a first contact pin operating per a first memory card standard upon horizontal insertion of the memory card in a first host device card slot, and the second portion configured to be contacted by a second contact pin operating per the first memory card standard upon vertical insertion of the memory card in a second host device card slot.

8. The memory card of claim 7 , wherein the interface pads are provided on a single side of the memory card.

9. The memory card of claim 7 , wherein the interface pads are provided on opposed sides of the memory card.

10. The memory card of claim 7 , wherein the first memory card standard is an SD memory card standard.

11. The memory card of claim 7 , wherein the first memory card standard is a PCIe memory card standard.

12. The memory card of claim 7 , wherein the interface pads are configured to mate with contact pins of a host device card slot operating per a combination of PCIe and SD memory card standards.

13. The memory card of claim 7 , wherein the first memory card standard is a Multimedia Card memory card standard.

14. The memory card of claim 7 , wherein the first memory card standard is a nano SIM card standard.

15. A memory card, comprising:

a first plurality of interface pads on a surface of the memory card, the first plurality of interface pads positioned to a first side of a central portion of the surface of the card and outside of the central portion;

a second plurality of interface pads on the surface of the memory card, the second plurality of interface pads positioned to a second side of a central portion and outside of the central portion; and

a third plurality of interface pads on the surface of the memory card, the third plurality of interface pads positioned entirely with central portion between the first and second pluralities of interface pads, the third plurality of interface pads comprising an interface pad having a first portion formed at an angle to a second portion;

wherein the first and second pluralities of interface pads are configured to mate with contact pins of first and second host device card slots operating per a first memory card standard, and the third plurality of interface pins are configured to mate with contact pins of the first and second host device card slots operating per a second memory card standard different than the first memory card standard;

wherein the first portion of the interface pad of the third plurality of interface pads is configured to be contacted by a contact pin operating per the second memory card standard upon horizontal insertion of the memory card in the first host device card slot; and

wherein the second portion is configured to be contacted by a contact pin operating per the second memory card standard upon vertical insertion of the memory card in the second host device card slot.

16. The memory card of claim 15 , wherein the first and second pluralities of interface pads are configured to mate with contact pins of the first and second host device card slots operating per a SD memory card standard.

17. The memory card of claim 15 , wherein the first and second pluralities of interface pads are configured to mate with contact pins of the first and second host device card slots operating per an MMC memory card standard.

18. The memory card of claim 15 , wherein the first and second pluralities of interface pads are configured to mate with contact pins of the first and second host device card slots operating per a nano SIM card standard.

19. The memory card of claim 15 , wherein the third plurality of interface pins are configured to mate with contact pins of the first and second host device card slots operating per a PCIe memory card standard.

20. A memory card, comprising:

first pad means for mating with contact pins of a host device card slot operating per a PCI Express (PCIe) memory card standard; and

second pad means for mating with contact pins of a host device card slot operating per a second memory card standard different than the PCIe memory card standard;

wherein at least one of the first pad means and second pad means include a first portion and a second portion at a right angle to the first portion;

wherein the first portion is configured to be contacted by a contact pin operating per one of the PCIe memory card standard and the second memory card standard upon horizontal insertion of the memory card in a first host device card slot; and

wherein the second portion is configured to be contacted by a contact pin operating per the same one of the PCIe memory card standard and the second memory card standard upon vertical insertion of the memory card in a second host device card slot.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2019
From: PINTO, YOSI; SIRAJUDEEN, SHAJITH MUSALIAR
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 048797/0792 →