IP Library Granted Patent US 11,822,814
Granted Patent B2
US 11,822,814 · App. 17/682,640 · Granted Nov 21, 2023

Dynamic XOR bin mapping in memory devices

Inventors: Shrinidhi Srikanth Kulkarni (Karnataka, IN); Vinayak Bhat (Karnataka, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/0655G06F3/0604G06F3/0679G11B20/1883
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Quick Facts
Patent No.
US 11,822,814
App. No.
17/682,640
Granted
Nov 21, 2023
Kind
B2
Abstract

A storage device includes multiple memory dies and a controller configured to: (i) perform XOR parity computations for parity bins based, at least in part, on updated contents of a first user data memory cell and contents of each user data memory cell also assigned to the first parity bin, (ii) storing the first parity data into a first parity memory cell associated with the first parity bin; (iii) identify a second parity memory cell for dynamic reconfiguration based, at least in part, on performance data of the non-volatile memory device, the second parity memory cell being assigned to a second parity bin; (iv) copy the second parity memory cell to a third memory cell of the plurality of memory cells; and (v) associate the third memory cell with the second parity bin, thereby making the third memory cell a parity memory cell of the plurality of parity memory cells.

Claims (59)

1. A method, comprising:

identifying a plurality of parity bins associated with a non-volatile memory device, the non-volatile memory device including a plurality of memory cells;

assigning a first subset of memory cells from the plurality of memory cells to store user data, thereby defining a plurality of user data memory cells and a remainder subset of memory cells;

assigning one memory cell from the remainder subset of memory cells to each parity bin of the plurality of parity bins, thereby defining a plurality of parity memory cells configured to store parity data;

assigning each user data memory cell of the plurality of user data memory cells to one of the parity bins of the plurality of parity bins;

performing exclusive-OR (XOR) parity computations during a write operation to a first user data memory cell that is assigned to a first parity bin, the XOR parity computations generating first parity data based, at least in part, on updated contents of the first user data memory cell and contents of each user data memory cell also assigned to the first parity bin, the XOR parity computations including storing the first parity data into a first parity memory cell associated with the first parity bin;

identifying a second parity memory cell for dynamic reconfiguration based, at least in part, on performance data of the non-volatile memory device, the second parity memory cell being assigned to a second parity bin;

copying the second parity memory cell to a third memory cell of the plurality of memory cells; and

associating the third memory cell with the second parity bin, thereby making the third memory cell a parity memory cell of the plurality of parity memory cells.

2. The method of claim 1 , further comprising dissociating the second memory cell from the second parity bin, thereby making the second memory cell unused.

3. The method of claim 1 , further comprising establishing a mirrored pair between the second parity memory cell to the third memory cell that causes any changes to one of the mirrored pair to the other of the mirrored pair.

4. The method of claim 1 , further comprising:

identifying a fourth parity bin that is adjacent in an assignment order to a fourth memory cell that is physically adjacent to the second memory cell; and

associating the second memory cell with the fourth parity bin, thereby making the second memory cell into a user data memory cell of the plurality of user data memory cells.

5. The method of claim 1 , further comprising:

identifying a dynamic reconfiguration trigger condition that defines when a dynamic reconfiguration of parity data is to be performed on the non-volatile memory device, the dynamic reconfiguration trigger condition identifying a first performance metric for the non-volatile memory device and an associated threshold value,

wherein identifying a second parity memory cell for dynamic reconfiguration includes detecting occurrence of the dynamic reconfiguration trigger condition based, at least in part, on performance data for components of the non-volatile memory device.

6. The method of claim 5 , wherein the threshold value of the dynamic reconfiguration trigger condition is a relative threshold value, wherein detecting occurrence of the dynamic reconfiguration trigger condition is based on comparing a difference value between two sub-components of the non-volatile memory device with respect to the first performance metric, the dynamic reconfiguration trigger condition being satisfied when the difference value exceeds the relative threshold value.

7. The method of claim 1 , further comprising:

monitoring one or more load performance characteristics associated with the non-volatile memory device; and

initiating the copying when the one or more load performance characteristics are below a predetermined threshold.

8. A storage device, comprising:

a non-volatile storage device comprising a plurality of memory dies, the non-volatile memory device including a plurality of memory cells; and

a controller communicatively coupled to the non-volatile storage device and configured to:

identify a plurality of parity bins associated with a non-volatile memory device;

assign a first subset of memory cells from the plurality of memory cells to store user data, thereby defining a plurality of user data memory cells and a remainder subset of memory cells;

assign one memory cell from the remainder subset of memory cells to each parity bin of the plurality of parity bins, thereby defining a plurality of parity memory cells configured to store parity data;

assign each user data memory cell of the plurality of user data memory cells to one of the parity bins of the plurality of parity bins;

perform exclusive-OR (XOR) parity computations during a write operation to a first user data memory cell that is assigned to a first parity bin, the XOR parity computations generating first parity data based, at least in part, on updated contents of the first user data memory cell and contents of each user data memory cell also assigned to the first parity bin, the XOR parity computations including storing the first parity data into a first parity memory cell associated with the first parity bin;

identify a second parity memory cell for dynamic reconfiguration based, at least in part, on performance data of the non-volatile memory device, the second parity memory cell being assigned to a second parity bin;

copy the second parity memory cell to a third memory cell of the plurality of memory cells; and

associate the third memory cell with the second parity bin, thereby making the third memory cell a parity memory cell of the plurality of parity memory cells.

9. The storage device of claim 8 , wherein the controller is further configured to dissociate the second memory cell from the second parity bin, thereby making the second memory cell unused.

10. The storage device of claim 8 , wherein the controller is further configured to establish a mirrored pair between the second parity memory cell to the third memory cell that causes any changes to one of the mirrored pair to the other of the mirrored pair.

11. The storage device of claim 8 , wherein the controller is further configured to:

identify a fourth parity bin that is adjacent in an assignment order to a fourth memory cell that is physically adjacent to the second memory cell; and

associate the second memory cell with the fourth parity bin, thereby making the second memory cell into a user data memory cell of the plurality of user data memory cells.

12. The storage device of claim 8 , wherein the controller is further configured to:

identify a dynamic reconfiguration trigger condition that defines when a dynamic reconfiguration of parity data is to be performed on the non-volatile memory device, the dynamic reconfiguration trigger condition identifying a first performance metric for the non-volatile memory device and an associated threshold value,

wherein identifying a second parity memory cell for dynamic reconfiguration includes detecting occurrence of the dynamic reconfiguration trigger condition based, at least in part, on performance data for components of the non-volatile memory device.

13. The storage device of claim 12 , wherein the threshold value of the dynamic reconfiguration trigger condition is a relative threshold value, wherein detecting occurrence of the dynamic reconfiguration trigger condition is based on comparing a difference value between two sub-components of the non-volatile memory device with respect to the first performance metric, the dynamic reconfiguration trigger condition being satisfied when the difference value exceeds the relative threshold value.

14. The storage device of claim 8 , wherein the controller is further configured to:

monitor one or more load performance characteristics associated with the non-volatile memory device; and

initiate the copying when the one or more load performance characteristics are below a predetermined threshold.

15. A storage device, comprising:

a non-volatile storage device comprising a plurality of memory dies, the non-volatile memory device including a plurality of memory cells; and

means for performing exclusive-OR (XOR) parity computations on the non-volatile memory device between a plurality of user data memory cells and a plurality of parity memory cells based, at least in part, on assignment of one parity bin of a plurality of parity bins to each memory cell of the plurality of user data memory cells and the plurality of parity memory cells;

means for identifying a first parity memory cell for dynamic reconfiguration based, at least in part, on performance data of the non-volatile memory device, the first parity memory cell being assigned to a first parity bin;

means for copying the first parity memory cell to a second memory cell of the plurality of memory cells; and

means for associating the second memory cell with the first parity bin, thereby making the second memory cell a parity memory cell of the plurality of parity memory cells.

16. The storage device of claim 15 , further comprising means for dissociating the first memory cell from the first parity bin, thereby making the first memory cell unused.

17. The storage device of claim 15 , means for establishing a mirrored pair between the first parity memory cell to the second memory cell that causes any changes to one of the mirrored pair to the other of the mirrored pair.

18. The storage device of claim 15 , further comprising:

means for identifying a second parity bin that is adjacent in an assignment order to a third memory cell that is physically adjacent to the first memory cell; and

means for associating the first memory cell with the second parity bin, thereby making the first memory cell into a user data memory cell of the plurality of user data memory cells.

19. The storage device of claim 15 , further comprising:

means for identifying a dynamic reconfiguration trigger condition that defines when a dynamic reconfiguration of parity data is to be performed on the non-volatile memory device, the dynamic reconfiguration trigger condition identifying a first performance metric for the non-volatile memory device and an associated threshold value,

wherein identifying a second parity memory cell for dynamic reconfiguration includes detecting occurrence of the dynamic reconfiguration trigger condition based, at least in part, on performance data for components of the non-volatile memory device.

20. The storage device of claim 19 , wherein the threshold value of the dynamic reconfiguration trigger condition is a relative threshold value, wherein detecting occurrence of the dynamic reconfiguration trigger condition is based on comparing a difference value between two sub-components of the non-volatile memory device with respect to the first performance metric, the dynamic reconfiguration trigger condition being satisfied when the difference value exceeds the relative threshold value.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2022
From: KULKARNI, SHRINIDHI SRIKANTH; BHAT, VINAYAK
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059120/0273 →