Test controller enabling a snapshot restore and resume operation within a device under test
Techniques are provided for capturing a processing state snapshot of a device under test (DUT) that enable a previous test run to be restored and resumed from the same point the snapshot was taken. The techniques enable restoring the snapshot into the same or a different device to resume a previous test run. In an illustrative example, a DUT is controlled by a Joint Test Action Group (JTAG) test controller to capture a Steady State Snapshot by controlling peripheral components of the DUT to complete any on-going tasks to reach a steady state and then flush data to a memory of the DUT. The flushed steady state peripheral component data and other processing state data is transferred to the test controller for analysis and for enabling the subsequent restore and resume operation. Solid state drive (SSD) examples are provided.
1. A test controller comprising:
an interface configured to connect the test controller to a device under test (DUT); and
a processing system coupled to the interface and configured to:
receive an indication of a processing point within processor code for obtaining data from the DUT for use with a subsequent resume processing operation;
control the DUT to run the processor code using a control processor of the DUT and perform a peripheral component task using a peripheral component of the DUT;
control the DUT to complete the peripheral component task in response to the control processor advancing to the processing point in the processor code; and
save, or control the DUT to save, completed peripheral component task data in a memory to enable the test controller to perform the subsequent resume processing operation.
2. The test controller of claim 1 , wherein the processing system is further configured to receive the indication of the processing point from a user of the test controller.
3. The test controller of claim 1 , wherein the peripheral component is one of a plurality of peripheral components of the DUT, each configured to perform a peripheral component task, and wherein the processing system is further configured to control the DUT to complete all peripheral component tasks of the plurality of peripheral components and save all completed peripheral component task data in the memory.
4. The test controller of claim 1 , wherein the processing system is further configured to control the peripheral component of the DUT to complete the peripheral component task by being further configured to control the peripheral component to process all pending peripheral component commands to reach a steady state.
5. The test controller of claim 4 , wherein the peripheral component includes a command queue and wherein the processing system is further configured to control the peripheral component to process pending peripheral component commands to reach the steady state by being configured to control the peripheral component to process all pending commands in its command queue.
6. The test controller of claim 4 , wherein the peripheral component commands comprise one or more of: tasks issued by the control processor of the DUT; and messages received by the DUT from an external device.
7. The test controller of claim 1 , wherein the processing system is further configured to control the peripheral component to output its completed peripheral component task data to the memory by being configured to apply a flush command to the peripheral component.
8. The test controller of claim 1 , wherein the DUT is configured for use with Joint Test Action Group (JTAG) test protocols, and wherein the processing system further is configured to apply JTAG control signals to the DUT to transfer the data to the test controller.
9. The test controller of claim 1 , wherein the memory is configured to store processing state data representative of a processing state of the control processor of the DUT, and wherein the processing system is further configured to obtain the processing state data from the memory to further enable the subsequent resume processing operation.
10. The test controller of claim 1 , wherein the processing system is further configured to process completed peripheral component task data obtained from the DUT as part of a debug procedure.
11. The test controller of claim 1 , wherein the processing system is further configured to perform the subsequent resume processing operation by being configured to:
initialize the DUT to run in a normal processing mode;
restore completed peripheral component task data obtained from the DUT into the same DUT; and
control the DUT to resume processing at the processing point using the restored data.
12. The test controller of claim 1 , wherein the DUT is a first DUT and the processing system is further configured to resume the processing operations within a second DUT.
13. The test controller of claim 12 , wherein the first DUT and the second DUT both comprise a data storage device (DSD) with a non-volatile memory (NVM), and wherein the processing system is further configured to transfer all data stored within the NVM of the first DUT to an external memory and then transfer the data to the NVM of the second DUT.
14. A method for use by a test controller, the method comprising:
receiving an indication of a processing point within processor code for obtaining data from a device under test (DUT) for use with a subsequent resume processing operation;
controlling the DUT to run the processor code using a control processor of the DUT and perform a peripheral component task using a peripheral component of the DUT;
controlling the DUT to complete the peripheral component task in response to the control processor advancing to the processing point in the processor code; and
saving, or controlling the DUT to save, completed peripheral component task data in a memory to enable the test controller to perform the subsequent resume processing operation.
15. The method of claim 14 , wherein the peripheral component is one of a plurality of peripheral components of the DUT, each configured to perform a peripheral component task, and wherein the DUT is controlled to complete all peripheral component tasks and save all completed peripheral component task data in the memory.
16. The method of claim 14 , wherein controlling the peripheral component of the DUT to complete its task comprises controlling the peripheral component to process pending commands to reach a steady state, and wherein the commands comprise one or more of: tasks issued by the control processor of the DUT; and messages received by the DUT from an external device.
17. The method of claim 14 , wherein the memory also stores processing state data representative of a processing state of the control processor of the DUT, and wherein the method further comprises transferring the processing state data from the memory to the test controller to further enable the subsequent resume operation.
18. The method of claim 14 , further comprising performing the subsequent resume processing operation by:
initializing the DUT to run in a normal processing mode;
restoring completed peripheral component task data obtained from the DUT into the DUT; and
controlling the DUT to resume processing operations at the processing point using the restored data.
19. The method of claim 14 , wherein the subsequent resume processing operation is performed using a different DUT than the DUT from which the data was obtained.
20. An apparatus comprising:
means for receiving an indication of a processing point within processor code for obtaining data from a device under test (DUT) for use with a subsequent resume processing operation;
means for controlling the DUT to run the processor code using a control processor of the DUT and perform a peripheral component task using a peripheral component of the DUT;
means for controlling the DUT to complete the peripheral component task in response to the control processor advancing to the processing point in the processor code; and
means for saving, or controlling the DUT to save, completed peripheral component task data in a memory to enable the apparatus to perform the subsequent resume processing operation.
21. A device comprising:
an interface configured to connect the device to a test controller;
a peripheral component; and
a processing system coupled to the interface and configured to:
receive an indication from the test controller of a processing point within processor code for obtaining peripheral component task data from the peripheral component for use with a subsequent resume processing operation;
run the processor code while performing a peripheral component task using the peripheral component;
control the peripheral component, in response to advancing to the processing point in the processor code, to complete the peripheral component task; and
save completed peripheral component task data in a memory to enable the test controller to perform the subsequent resume processing operation.