IP Library Granted Patent US 10,884,628
Granted Patent B2
US 10,884,628 · App. 16/227,168 · Granted Jan 5, 2021

Performance of a read in a memory system

Inventors: Niles Yang (San Jose, CA); Phil Reusswig (San Jose, CA); Alexandra Bauche (San Jose, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/061G06F3/0655G06F3/0679
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Quick Facts
Patent No.
US 10,884,628
App. No.
16/227,168
Granted
Jan 5, 2021
Kind
B2
Abstract

Improving performance of a read in a memory system. Various methods include: reading data from a word line in a memory block, where during the read, associated parameters are generated that include: a value indicative of a throughput time, and a value indicative of a bit error rate (BER); retrieving the value indicative of the throughput time and the value indicative of the BER; and performing a read improvement process if the value indicative of the throughput time is above a threshold value. The method also includes performing the read improvement process by: flagging the memory block if the value indicative of the BER is at or below and expected BER; and performing cleanup operations if the value indicative of the BER is higher than the expected BER.

Claims (48)

1. A method of improving performance of a read in a memory system comprising:

reading data from a word line in a memory block, and generating associated parameters that include:

a value indicative of a throughput time, and

a value indicative of a bit error rate (BER);

retrieving the value indicative of the throughput time and the value indicative of the BER; and

performing a read improvement process if the value indicative of the throughput time is above a threshold value, the read improvement process comprising:

performing cleanup operations if the value indicative of the BER is higher than an expected BER, the cleanup operations comprising:

modifying a set of read parameters associated with the memory block, thereby creating modified read parameters,

reading test data from the word line using the modified read parameters and generating a value indicative of a test bit error rate,

determining if the value indicative of the test bit error rate is above a BER threshold, and

flagging the memory block if the value indicative of the BER is at or below the expected BER;

determining that a number of times the memory clock is flagged is above a threshold amount; and

performing the cleanup operations.

2. The method of claim 1 , the cleanup operations further comprising:

if the BER indicative value is not above the BER threshold, performing a read scrub that re-scrambles the data using a scrambling seed different from a prior scrambling seed and moves the data to a different location.

3. The method of claim 1 , further comprising retrieving the value indicative of the BER and the value indicative of the throughput time from registers of an error correction engine.

4. A non-transitory computer readable media storing instructions that are executable by a processor to cause a memory system to:

read data in a memory block, wherein:

the memory block includes a plurality of word lines, and

the data is located in a first word line of the plurality of word lines;

retrieve a value indicative of a throughput time and a value indicative of a bit error rate (BER), wherein the value indicative of the throughput time and the value indicative of the BER are generated based on the read; and

perform a read improvement process if the value indicative of the throughput time is above a threshold value, the read improvement process comprising:

performing cleanup operations if the value indicative of the BER is higher than an expected BER, the cleanup operations comprising:

modifying a set of read parameters associated with the memory block, thereby creating modified read parameters,

reading test data form the word line using the modified read parameters and generating a value indicative of a test bit error rate,

determining if the value indicative of the test bit error rate is above a BER threshold, and

flagging the memory block if the value indicative of the BER is at or below the expected BER;

determining that a number of times the memory clock is flagged is above a threshold amount; and

performing the cleanup operations.

5. The non-transitory computer-readable media of claim 4 , the cleanup operations further comprising:

if the BER indicative value is not above the BER threshold, performing a read scrub that re-scrambles the data using a scrambling seed different from a prior scrambling seed and moving the second data to a different location.

6. A non-volatile storage system comprising:

a memory array, wherein:

the memory array comprises a plurality of non-volatile memory cells arranged as memory blocks, and

a first memory block of the memory blocks includes a word line storing a first data; and

a controller coupled to the memory array, wherein the controller is configured to:

read the first data from the first memory block;

retrieve, from an error correction engine, a value indicative of a throughput time and a value indicative of a bit error rate (BER); and

perform a read improvement process if the value indicative of the throughput time is above a threshold value, the read improvement process comprising:

comprising performing cleanup operations if the value indicative of the BER is higher than an expected BER, the cleanup operations comprising:

modifying a set of read parameters associated with the first memory block, thereby creating modified read parameters,

reading test data form the word line using the modified read parameters and generating a value indicative of a test bit error rate,

determining if the value indicative of the test bit error rate is above a BER threshold, and

flagging the memory block if the value indicative of the BER is at or below the expected BER;

determining that a number of times the memory clock is flagged is above a threshold amount; and

performing the cleanup operations.

7. The non-volatile storage system of claim 6 , the cleanup operations further comprising:

if the BER indicative value is not above the expected BER, perform a read scrub that re-scrambles the data using a scrambling seed different from a prior scrambling seed and moves the first data to a different memory block.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2018
From: YANG, NILES; REUSSWIG, PHIL; BAUCHE, ALEXANDRA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 047830/0886 →
Continuity (1)
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