Redundancy of error correction encoded data in a storage system
View Patent ↗A device that provides for redundancy of error correction encoded data includes at least one processor circuit. The at least one processor circuit is configured to perform error correction encoding on data items to generate corresponding codewords, where at least one of the data items may have a different length than at least one other of the data items and each of the codewords is the same length. The at least one processor circuit is further configured to generate a redundancy data item based at least in part on the codewords. The at least one processor circuit is further configured to write the codewords and the redundancy data item to separate blocks of at least one flash memory circuit.
1. A device comprising:
at least one processor circuit configured to:
determine a plurality of code rates for encoding data based on integrities of each of a plurality of separate flash memory blocks;
perform error correction encoding on a plurality of data items to generate a plurality of codewords, wherein at least one of the plurality of data items comprises a different length than at least one other of the plurality of data items and each of the plurality of codewords comprises a same codeword length;
generate a redundancy data item based at least in part on performing an operation using multiple codewords of the plurality of codewords;
write each of the plurality of codewords to a respective one of flash memory blocks of a respective one of flash memory circuits; and
write the redundancy data item to at least one additional block in another flash memory circuit separate from the flash memory circuits, wherein the at least one additional block is separate from the flash memory blocks containing the plurality of codewords, and wherein an integrity of the at least one additional block is greater than a highest integrity of any of the plurality of separate flash memory blocks.
2. The device of claim 1 , wherein the plurality of data items are encoded at a plurality of code rates and at least one of the plurality of data items is encoded at a different code rate than at least one other of the plurality of data items.
3. The device of claim 2 , wherein the at least one processor circuit is further configured to:
receive a data stream from a host device; and
parse the data stream into the plurality of data items based at least in part on the plurality of code rates.
4. The device of claim 1 , wherein at least one of the plurality of codewords is recoverable using the redundancy data item in conjunction with other codewords of the plurality of codewords.
5. The device of claim 1 ; wherein the at least one processor circuit is further configured to generate the redundancy data item based at least in part on performing a bitwise exclusive-or operation on the plurality of codewords.
6. A computer program product comprising instructions stored in a tangible computer-readable storage medium, the instructions comprising:
instructions to retrieve, from each of a plurality of flash memory blocks, an associated codeword of a plurality of codewords, wherein at least one of the plurality of codewords is encoded at a different code rate of a plurality of code rates than at least one other of the plurality of codewords, the plurality of code rates is determined based on integrities of the plurality of flash memory blocks, and each of the plurality of codewords comprises a same codeword length;
instructions to perform error correction decoding on each of the plurality of codewords to generate a plurality of corrected codewords;
instructions to identify at least one of the plurality of codewords that cannot be properly decoded;
instructions to retrieve, from another block that is separate from the plurality of flash memory blocks, a redundancy data item, wherein the another block is retrieved from a flash memory circuit separate from a plurality of flash memory circuits storing the plurality of flash memory blocks; and
instructions to recover the at least one of the plurality of codewords that cannot be properly decoded based at least in part on the plurality of corrected codewords and the redundancy data item.
7. The computer program product of claim 6 , wherein the instructions further comprise:
instructions to retrieve a plurality of data items from bath the recovered at least one of the plurality of codewords and the plurality of corrected codewords; and
instructions to provide the plurality of data items to a host device.
8. The computer program product of claim 7 , wherein at least one of the plurality of data items comprises a different length than at least one other of the plurality of data items.
9. The computer program product of claim 6 , wherein the redundancy data item is not a valid codeword.
10. The computer program product of claim 6 , wherein the error correction decoding comprises low-density parity check error correction decoding.
11. A method comprising:
determining, for each block of a plurality of flash memory blocks, an associated code rate of a plurality of code rates based on an integrity of the flash memory block;
identifying, for each block of the plurality of flash memory blocks, a data item of a plurality of data items; the data item having a length that is determined based at least in part on the associated code rate of the plurality of code rates;
performing, on each data item of the plurality of data items; error correction encoding to generate, for each block of the plurality of flash memory blocks; an associated codeword of a plurality of codewords;
generating a redundancy data item based at least in part on each of the plurality of codewords;
writing, to each block of the plurality of flash memory blocks on a respective one of a plurality of flash memory blocks, the associated codeword; and
writing, to at least one additional block that is separate from the plurality of flash memory blocks, the redundancy data item without performing error correction encoding on the redundancy data item, wherein the at least one additional block is written to another flash memory circuit that is separate from the plurality of flash memory blocks, and wherein an integrity of the at least one additional block is greater than a highest integrity of the plurality of flash memory blocks.
12. The method of claim 11 , wherein a first code rate of the plurality of code rates associated with a first block of the plurality of flash memory blocks is different than a second code rate of the plurality of code rates associated with a second block of the plurality of flash memory blocks.
13. The method of claim 12 , wherein each of the plurality of codewords has a same codeword length.
14. The method of claim 11 , wherein at least one of the plurality of codewords is recoverable from other codewords of the plurality of codewords and the redundancy data item.
15. The method of claim 11 , wherein generating the redundancy data item based at least in part on each of the plurality of codewords further comprises generating the redundancy data item based at least in part on performing a bitwise exclusive-or operation on each of the plurality of codewords.
16. The method of claim 11 , further comprising:
receiving a data stream from a host device; and
parsing the data stream into the plurality of data items.