IP Library Granted Patent US 11,403,529
Granted Patent B2
US 11,403,529 · App. 16/022,116 · Granted Aug 2, 2022

Noise injection training for memory-based learning

Inventors: Minghai Qin (San Jose, CA); Dejan Vucinic (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
G06N3/084
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Quick Facts
Patent No.
US 11,403,529
App. No.
16/022,116
Granted
Aug 2, 2022
Kind
B2
Abstract

The system described herein can include neural networks with noise-injection layers. The noise-injection layers can enable the neural networks to be trained such that the neural networks are able to maintain their classification and prediction performance in the presence of noisy data signals. Once trained, the parameters from the neural networks with noise-injection layers can be used in the neural networks of systems that include resistive random-access memory (ReRAM), memristors, or phase change memory (PCM), which use analog signals that can introduce noise into the system. The use of ReRAM, memristors, or PCM can enable large-scale parallelism that improves the speed and computational efficiency of neural network training and classification. Using the parameters from the neural networks trained with noise-injection layers, enables the neural networks to make robust predictions and calculations in the presence of noisy data.

Claims (55)

1. A system comprising:

a memory comprising a plurality of memory cells, each of the memory cells configured to store one of a plurality of weights of a hidden layer of a neural network as a corresponding conductance value; and

one or more processing circuits, including a noise generator, coupled with the memory and configured to:

receive a plurality of input voltages for the hidden layer of the neural network, each of the input voltages corresponding to an output voltage of a preceding layer of the neural network;

generate, by the noise generator, one or more noise components;

add a corresponding one of the one or more noise components to each of the input voltages for the hidden layer of the neural network;

perform a matrix multiplication of the input voltages for the hidden layer of the neural network including the added corresponding noise component with the weights of the hidden layer of the neural network by applying each of the input voltages including the added corresponding noise component to a corresponding input of the memory;

determine a plurality of output voltages from the memory corresponding to the matrix multiplication of the input voltages for the hidden layer of the neural network including the added corresponding noise component with the weights of the hidden layer of the neural network; and

determine a classification based on the output voltages.

2. The system of claim 1 , wherein the plurality of memory cells comprises at least one of resistive random-access memory (ReRAM), memristors, or phase change memory (PCM).

3. The system of claim 1 , wherein the one or more processing circuits are further configured to:

receive the plurality of weights of the hidden layer of the neural network; and

each of the plurality of weights into a respective one of the plurality of memory cells as the corresponding conductance value.

4. The system of claim 1 , wherein the neural network is a recurrent neural network.

5. The system of claim 1 , wherein the neural network is a convolutional neural network.

6. The system of claim 1 , wherein the neural network is a long-short-memory neural network.

7. A system, comprising:

one or more processing circuits, including a noise generator, configured to couple to a plurality of memory cells of a resistive network, the one or more processing circuits further configured to:

receive a plurality of weights for a hidden layer of a neural network;

set each of the plurality of weights into a memory cell of the plurality of memory cells of the resistive network as a corresponding conductance value;

receive a plurality of input voltages for the hidden layer of the neural network, each of the input voltages corresponding to an output voltage of a preceding layer of the neural network;

generate, by the noise generator, one or more noise components;

add a corresponding one of the one or more noise components to each of the plurality of input voltages for the hidden layer of the neural network;

apply each of the plurality of input voltages including the added noise component for the hidden layer of the neural network to a corresponding input of the resistive network to thereby perform a matrix multiplication with the weights of the hidden layer of the neural network;

determine a plurality of output voltages corresponding to the matrix multiplication from the resistive network; and

determine a classification based on the plurality of output voltages.

8. The system of claim 7 , further comprising the resistive network, the resistive network comprising the plurality of memory cells.

9. The system of claim 8 , wherein each of the plurality of memory cells comprises at least one of resistive random-access memory (ReRAM), memristors, or phase change memory (PCM).

10. A method, comprising:

receiving a plurality of input voltages for a hidden layer of a neural network, each of the input voltages corresponding to an output voltage of a preceding layer of the neural network;

generating one or more noise components by a noise generator;

adding a corresponding one of the one or more noise components to each of the input voltages for the hidden layer of the neural network;

applying the input voltages including the added corresponding noise components to corresponding inputs of a memory comprising a plurality of memory cells, each of the memory cells configured to store one of a plurality of weights of a hidden layer of a neural network as a corresponding conductance value, to thereby perform a matrix multiplication of the weights of the hidden layer of the neural network with the input voltages including the added corresponding noise components;

determining a plurality of output voltages from the memory corresponding to the matrix multiplication of the weights of the hidden layer of the neural network with the input voltages including the added corresponding noise components; and

determining a classification based on the output voltages.

11. The method of claim 10 , wherein the plurality of memory cells are part of a resistive network, the method further comprising:

setting of the plurality of weights by loading the plurality of weights into the plurality of memory cells by setting the corresponding conductance value of each of respective plurality of memory cells in the resistive network.

12. The method of claim 10 , wherein the plurality of memory cells comprises at least one of resistive random-access memory (ReRAM), memristors, or phase change memory (PCM).

13. A method, comprising:

receiving a plurality of weights for a hidden layer of a neural network;

setting each of the plurality of weights into a memory cell of a resistive network as a corresponding conductance value;

generating one or more noise components by a noise generator;

receiving a plurality of input voltages for the hidden layer of the neural network, each of the input voltages corresponding to an output voltage of a preceding layer of the neural network;

adding a corresponding one of the one or more noise components to each of the plurality of input voltages for the hidden layer of the neural network;

applying each of the plurality input voltages including the added noise component for the hidden layer of the neural network to a corresponding input of the resistive network to thereby perform a matrix multiplication with the weight of the hidden layer of the neural network;

determining a plurality of output voltages corresponding to the matrix multiplication from the resistive network; and

determining a classification based on the plurality of output voltages.

14. The method of claim 13 , wherein each of the plurality of memory cells comprises at least one of a resistive random-access memory (ReRAM), memristors, or phase change memory (PCM).

15. The method of claim 13 , further comprising:

determining the plurality of weights, wherein determining the plurality of weights comprises determining the weight for each of the plurality of weights with back-propagation.

16. The method of claim 13 , wherein the noise component is one of Gaussian noise, Brownian noise, Poisson noise, Speckle noise, or Salt and Pepper noise.

17. The method of claim 13 , further comprising determining a plurality of biases for the neural network.

18. The method of claim 13 , wherein the neural network is a recurrent neural network.

19. The method of claim 13 , wherein the neural network is a convolutional neural network.

20. The method of claim 13 , wherein the neural network is a long-short-memory neural network.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2018
From: QIN, MINGHAI; VUCINIC, DEJAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046241/0620 →