Apparatus and method for reducing storage class memory write-backs
View Patent ↗Embodiments of the present disclosure perform procedures that manipulate a memory system's local cache line eviction policy so that critical “dirty” cache lines are evicted from last level caches as late as possible. Embodiments can selectively handle cache lines in a manner that can renew the liveliness of “dirty” cache lines so that a local “least recently used” (LRU) eviction policy treats them as though they were recently accessed rather than evicting them. Embodiments perform read operations and manipulate the age or “active” status of cache lines by performing procedures which modify “dirty” cache lines to make them appear active to the processor. Embodiments of the present disclosure can also invalidate “clean” cache lines so that “dirty” lines automatically stay in the cache.
1. A method of storing data in memory, said method comprising:
determining if a data request generates a cache miss in a memory resident on a computer system, said memory comprising a plurality of different cache memory levels and a main memory;
identifying a first cache line subject to displacement from a first cache memory level responsive to said first cache memory level storing a new entry corresponding to said data request, wherein the identifying a first cache line subject to displacement from said first cache memory level occurs when said data request generates said cache miss in a first cache memory level of said plurality of different cache memory levels; and
activating said first cache line within said first cache memory level to retain data stored therein to delay a write operation of said new entry to said main memory, wherein activating said first cache line further comprises generating a helper thread configured to perform touch operations on a cache memory level storing said first cache line.
2. The method of storing data in memory as described in claim 1 , wherein said first cache line is dirty.
3. The method of storing data in memory as described in claim 1 , wherein activating said first cache line further comprises generating a helper thread configured to perform invalidation operations on clean cache lines stored in said cache memory level.
4. The method of storing data in memory as described in claim 3 , wherein generating the helper thread configured to perform invalidating operations further comprises invalidating operations of a main thread processing instructions related to said first cache line.
5. The method of storing data in memory as described in claim 3 , wherein invalidating operations of a main thread further comprises performing said invalidating operations concurrent to execution of said main thread.
6. A system for storing data in memory, said system comprising:
a memory resident on a computer system, said memory comprising a plurality of different cache memory levels and a main memory, each cache memory level comprising a plurality of different cache lines;
a cache line controller module configured to determine if a data request generates a cache miss in a first cache memory level of said plurality of different cache memory levels, said cache line controller module configured to identify a first cache line subject to displacement from said first cache memory level responsive to said first cache memory level storing a new entry corresponding to said data request, wherein said first cache line is dirty;
a cache line activation module configured to activate said first cache line within said first cache memory level to retain data stored therein to delay a write operation of said new entry to said main memory; and
a helper thread generation module configured to generate a helper thread to perform touch operations on a cache memory level storing said first cache line.
7. The system for storing data in memory as described in claim 6 , wherein the cache line controller module is configured to identify a first cache line subject to displacement from said first cache memory level when said data request generates said cache miss in a first cache memory level of said plurality of different cache memory levels.
8. The system for storing data in memory as described in claim 6 , wherein said helper thread is configured to perform invalidation operations on clean cache lines stored in said cache memory level.
9. The system for storing data in memory as described in claim 8 , wherein said helper thread is configured to invalidate operations of a main thread processing instructions related to said first cache line.
10. The system for storing data in memory as described in claim 9 , wherein said helper thread is configured to invalidate operations concurrent to execution of said main thread.
11. A method of storing data in memory, said method comprising:
receiving a data request to perform an operation using memory resident on a computer system, said memory comprising a plurality of different cache memory levels;
performing a first read to determine if said data request generates a cache miss in a first cache memory level of said plurality of different cache memory levels;
when said data request generates a cache miss in said first cache memory level, selecting a first cache line within said first cache memory level to store a new entry corresponding to said data request, thereby subjecting a second cache line to displacement from said first cache memory level; and
when said second cache line currently stores a dirty entry, performing a second read of said second cache line, said second read comprising computer-implemented procedures to make said second cache line active within said first cache memory level to retain data stored therein and delay a write operation of said new entry to a second cache memory level of said plurality of different cache memory levels, wherein said performing a second read further comprises calculating a ratio between clean cache lines and dirty cache lines on a cache memory level storing said second cache line to determine performance of activation procedures, and wherein, when said cache memory level comprises less dirty cache lines than clean cache lines, generating a helper thread to perform touch operations on a cache memory level storing said second cache line.
12. The method of storing data in memory as described in claim 11 , wherein, when said cache memory level comprises more dirty cache lines than clean cache lines, generating a helper thread to perform invalidation operations on a cache memory level storing said second cache line.
13. The method of storing data in memory as described in claim 12 , wherein generating a helper thread configured to perform invalidating operations further comprises performing invalidation operations on clean cache lines stored in said cache memory level.
14. The method of storing data in memory as described in claim 12 , wherein performing invalidation operations further comprises invalidating operations of a main thread processing instructions related to said first cache line.