IP Library Granted Patent US 12,131,058
Granted Patent B2
US 12,131,058 · App. 17/726,755 · Granted Oct 29, 2024

Configurable arithmetic HW accelerator

Inventors: Yuri Ryabinin (Beer Sheva, IL); Shay Benisty (Beer Sheva, IL)
Assignee: Sandisk Technologies, Inc.
G06F3/0655G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 12,131,058
App. No.
17/726,755
Granted
Oct 29, 2024
Kind
B2
Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller includes a decoder multiplexer (mux) module, a plurality of request/response channels coupled to the decoder mux module, an arithmetic pipeline module coupled to the plurality of request/response channels, an arbiter module coupled to the plurality of request/response channels and the arithmetic pipeline module, a mux/arbiter module coupled to the arithmetic pipeline module, a random access memory (RAM) access module coupled to the decoder mux module and the mux/arbiter module, and a RAM coupled to the mux/arbiter module. The controller is configured to determine a pipeline depth value and a calculation parallelism value of the arithmetic pipeline module and configure the arithmetic pipeline module based on the determining.

Claims (23)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller comprises:

a decoder module;

a plurality of response channels coupled to the decoder module;

an arithmetic pipeline module coupled to the plurality of response channels;

an arbiter module coupled to the plurality of response channels and the arithmetic pipeline module;

a mux module coupled to the arithmetic pipeline module;

a random access memory (RAM) access module coupled to the decoder module and the mux module; and

a RAM coupled to the mux module.

2. The data storage device of claim 1 , wherein the controller is configured to store static parameters and deliver the static parameters to the arithmetic pipeline module, wherein the arithmetic pipeline module is disposed in a calculation accelerator module of the controller.

3. The data storage device of claim 1 , wherein the controller is configured to determine a calculation configuration based on a received input and provide the calculation configuration to the arithmetic pipeline module of a calculation module of the controller.

4. The data storage device of claim 3 , wherein one or more static parameters are provided to the arithmetic pipeline module based on the calculation configuration.

5. The data storage device of claim 3 , wherein the calculation configuration comprises one or more definitions to set a structure of the arithmetic pipeline module and set an order of calculations of the arithmetic pipeline module.

6. The data storage device of claim 5 , wherein the structure of the arithmetic pipeline module is configurable based on calculation parallelism value and pipeline depth value, wherein the structure comprises a plurality of stages, and wherein a number of the plurality of stages is configurable based on the calculation parallelism value and the pipeline depth value.

7. The data storage device of claim 6 , wherein the controller is configured to, for each stage of the plurality of stages, perform a plurality of arithmetic calculations based on the order of calculations.

8. The data storage device of claim 7 , wherein results of the plurality of arithmetic calculations are provided to a next stage of the plurality of stages, and wherein last results of the plurality of arithmetic calculations are sent to the plurality of response channels.

9. The data storage device of claim 1 , wherein the controller is configured to use the plurality of response channels to activate the arithmetic pipeline module and to receive calculation results from the arithmetic pipeline module.

10. The data storage device of claim 1 , wherein the controller further comprises a plurality of central processing units (CPUs), and wherein each CPU is associated with a request/response channel of the plurality of response channels.

11. The data storage device of claim 1 , wherein the arbiter module is configured to:

arbitrate between the plurality of response channels when a threshold number of outstanding requests of the arithmetic pipeline module is exceeded; and

provide an outstanding request to the arithmetic pipeline module based on the arbitrating.

12. The data storage device of claim 1 , wherein the controller is configured to store configurations/databases that are greater than a threshold size in the RAM.

Assignments (8)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2022
From: RYABININ, YURI; BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059679/0693 →
Continuity (1)
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