IP Library Granted Patent US 12,341,130
Granted Patent B2
US 12,341,130 · App. 17/658,447 · Granted Jun 24, 2025

Method of thinning a semiconductor die

Inventors: Meiqin Hao (Shanghai, CN); Izzie Zhang (Shanghai, CN); Elley Zhang (Shanghai, CN); Thierry Du (Shanghai, CN); Maggie Deng (Shanghai, CN); Bo Fu (Shanghai, CN); Caiden Zhong (Shanghai, CN)
Assignee: Western Digital Technologies, Inc.
H01L25/0657H01L21/463H01L21/4853H01L21/563H01L24/11
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Quick Facts
Patent No.
US 12,341,130
App. No.
17/658,447
Granted
Jun 24, 2025
Kind
B2
Abstract

A method for thinning a semiconductor die includes providing the semiconductor die having electrical contacts electrically connected to and protruding from a top surface of the semiconductor die. The electrical contacts are spaced from one another on the top surface of the semiconductor die. The electrical contacts are encapsulated and a portion of the top surface of the semiconductor die is covered by a semisolid filler. The semisolid filler fills the space between the electrical contacts. An adhesive layer is applied to a top surface of the semisolid filler, and a backgrinding process is performed on a bottom surface of the semiconductor die. The method allows for thin semiconductor dies to be manufactured while reducing the risk of manufacturing defects associated with backgrinding.

Claims (19)

1. A method for thinning a semiconductor die, the method comprising:

providing a semiconductor die having a top planar surface, a bottom planar surface opposite the top planar surface, and a plurality of electrical contacts electrically connected to and protruding from the top planar surface, each electrical contact of the plurality of electrical contacts spaced from one another on the top planar surface of the semiconductor die;

encapsulating the plurality of electrical contacts and covering at least a portion of the top planar surface of the semiconductor die with a semisolid filler, wherein the semisolid filler fills the space between the electrical contacts and fills a space above the electrical contacts defined by a top surface of the semisolid filler, wherein the top surface of the semisolid filler has a first height from the top planar surface of the semiconductor die that is greater than a second height of the electrical contacts from the top planar surface of the semiconductor die;

applying an adhesive layer to the top surface of the semisolid filler after the semisolid filler has hardened to a solid state, causing the adhesive layer to be in contact with the top surface of the semisolid filler at the first height;

performing a backgrinding process on the bottom planar surface of the semiconductor die after applying the adhesive layer, wherein performing the backgrinding process includes backgrinding the bottom planar surface of the semiconductor die until the semiconductor die has a decreased thickness measured in a direction perpendicular to the bottom planar surface; and

removing the adhesive layer from the semiconductor die after performing the backgrinding process, wherein removing the adhesive layer from the semiconductor die causes the semisolid filler to be removed from the semiconductor die.

2. The method of claim 1 , wherein an adhesion strength of the adhesive layer to the semisolid filler is greater than an adhesion strength of the semisolid filler to the plurality of electrical contacts and the top planar surface of the semiconductor die.

3. The method of claim 1 , wherein the decreased thickness is 45-55 micrometers.

4. The method of claim 1 , wherein the semiconductor die following the backgrinding process has a total thickness variation of less than 3 micrometers.

5. The method of claim 1 , wherein the semisolid filler is a mixture including alginate.

6. A method for thinning a semiconductor die comprising a solder joint array including a plurality of solder bumps, the method comprising:

applying a semisolid filler to the plurality of solder bumps, wherein the semisolid filler encapsulates the solder bumps, fills gaps between the solder bumps, and fills a space above the solder bumps defined by a top surface of the semisolid filler, wherein the top surface of the semisolid filler has a first height from a top planar surface of the semiconductor die that is a greater than a second height of the solder bumps from the top planar surface of the semiconductor die;

applying backgrinding tape to the top surface of the semisolid filler after the semisolid filler has hardened to a solid state, causing the backgrinding tape to be in contact with the top surface of the semisolid filler at the first height;

performing a backgrinding process on a bottom planar surface of the semiconductor die after applying the backgrinding tape, wherein performing the backgrinding process includes backgrinding the bottom planar surface of the semiconductor die until the semiconductor die has a decreased thickness measured in a direction perpendicular to the bottom planar surface; and

removing the backgrinding tape from the semiconductor die after performing the backgrinding process, wherein removing the backgrinding tape from the semiconductor die causes the semisolid filler to be removed from the semiconductor die.

7. The method of claim 6 , wherein an adhesion strength of the backgrinding tape to the semisolid filler is greater than an adhesion strength of the semisolid filler to the plurality of solder bumps.

8. The method of claim 6 , wherein the decreased thickness is 45-55 micrometers.

9. The method of claim 6 , wherein the semiconductor die following the backgrinding process has a total thickness variation of less than 3 micrometers.

10. The method of claim 6 , wherein the semisolid filler is a mixture including alginate.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2022
From: HAO, MEIQIN; ZHANG, IZZIE; ZHANG, ELLEY; DU, THEIRRY; DENG, MAGGIE; FU, BO; ZHONG, CAIDEN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059774/0313 →