IP Library Granted Patent US 11,874,770
Granted Patent B2
US 11,874,770 · App. 17/743,285 · Granted Jan 16, 2024

Indexless logical-to-physical translation table

Inventors: Oleg Kragel (San Jose, CA); Vijay Sivasankaran (Dublin, CA)
Assignee: Western Digital Technologies, Inc.
G06F12/0246G06F2212/7201
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Quick Facts
Patent No.
US 11,874,770
App. No.
17/743,285
Granted
Jan 16, 2024
Kind
B2
Abstract

An indexless logical-to-physical translation table (L2PTT). In one example, the data storage device including a memory, a data storage controller, and a bus. The memory including a mapping unit staging page that includes a plurality of mapping unit pages and a mapping unit page directory. The data storage controller including a data storage controller memory and coupled to the memory, the data storage controller memory including an indexless logical-to-physical translation table (L2PTT). The bus for transferring data between the data storage controller and a host device in communication with the data storage controller. The data storage controller is configured to perform one or more memory operations with the indexless L2PTT.

Claims (72)

1. A data storage device comprising:

a memory including a mapping unit staging page that includes i) a plurality of mapping unit pages and ii) a mapping unit page directory;

a data storage controller including a data storage controller memory, the data storage controller coupled to the memory, and the data storage controller memory including an indexless logical-to-physical translation table (L2PTT); and

a bus for transferring data between the data storage controller and a host device in communication with the data storage controller,

wherein the data storage controller is configured to perform one or more memory operations with the indexless L2PTT.

2. The data storage device of claim 1 , wherein the one or more memory operations include at least one of:

an indexless L2PTT update operation,

a closed indexless L2PTT flash block compaction operation, or

an indexless L2PTT initialization operation after a graceful shutdown.

3. The data storage device of claim 2 , wherein the indexless L2PTT update operation is an operation to program an updated mapping unit page to a write-open flash block.

4. The data storage device of claim 2 , wherein the indexless L2PTT update operation includes:

identifying a free slot in the mapping unit staging page,

copying a mapping unit page from the indexless L2PTT to the identified free slot in the mapping unit staging page, and

recording a mapping unit page index, associated with the copied mapping unit page, in the mapping unit page directory in the mapping unit staging page.

5. The data storage device of claim 2 , wherein the closed indexless L2PTT flash block compaction operation includes i) programming, at least one component of the indexless L2PTT that is still valid in source compaction flash block, to a destination flash block and ii) performing source flash block recycling.

6. The data storage device of claim 2 , wherein the closed indexless L2PTT flash block compaction operation includes the data storage controller configured to:

determine, with a mapping unit page location index, a set of mapping unit pages, wherein each mapping unit page, included in the set of mapping unit pages is valid, and

store the each mapping unit page, included in the set of mapping unit pages, into the mapping unit staging page.

7. The data storage device of claim 2 , wherein the indexless L2PTT initialization operation is a serial initialization operation.

8. The data storage device of claim 7 , wherein the memory includes a list of flash blocks dedicated for L2PTT storage, wherein the data storage controller memory further includes a mapping unit page location index, and wherein the serial initialization operation includes the data storage controller configured to:

determine, with the mapping unit page directory, a set of mapping unit pages staged in the mapping unit staging page,

process the mapping unit page directory, and

for each mapping unit page index included in the mapping unit page directory,

determine whether a record in the mapping unit page location index has been initialized,

when the record in the mapping unit page location index has not been initialized, initialize the record, in the mapping unit page location index, with a relative index of a corresponding flash block in the list of flash blocks dedicated for L2PTT storage, and

copy content of a mapping unit page from a location of the mapping unit page, in the mapping unit staging page, to a corresponding location in the indexless L2PTT.

9. The data storage device of claim 2 , wherein the indexless L2PTT initialization operation is a parallel initialization operation.

10. The data storage device of claim 9 , wherein the memory includes a list of flash blocks dedicated for L2PTT storage, wherein the data storage controller memory further includes a mapping unit page location index, and wherein the parallel initialization operation includes the data storage controller configured to:

determine, using the mapping unit page directory, a set of mapping unit pages from the plurality of mapping unit pages that are staged in the mapping unit staging page, process the mapping unit page directory, and

for each mapping unit page index included in the mapping unit page directory,

determine whether a record in the mapping unit page location index has been initialized,

when the record in the mapping unit page location index has been initialized, compare i) a first flash block location of a mapping unit page being processed with ii a second flash block location saved in an auxiliary data structure storing latest flash block locations of each mapping unit page, to determine whether the mapping unit page has been initialized,

when the mapping unit page has not been initialized,

initialize the record, in the mapping unit page location index, with a relative index of a corresponding flash block in the list of flash blocks dedicated for L2PTT storage, and

save, in the auxiliary data structure, the first flash block location of the mapping unit page being processed, and

copy content of the mapping unit page from a location of the mapping unit page, in the mapping unit staging page, to a corresponding location in the indexless L2PTT.

11. The data storage device of claim 10 , wherein the data storage controller is configured to determine that the mapping unit page is uninitialized when the first flash block location, of the mapping unit page being processed, was written after the second flash block location was saved in the auxiliary data structure.

12. The data storage device of claim 10 , wherein the data storage controller is configured to determine that the mapping unit page is initialized when the first flash block location, of the mapping unit page being processed, was written after before the second flash block location was saved in the auxiliary data structure.

13. A method comprising:

generating, with a data storage controller, an indexless logical-to-physical translation table (L2PTT) in a data storage controller memory of the data storage controller;

staging, with the data storage controller, a mapping unit staging page, based on the indexless L2PTT, in a memory, the mapping unit staging page including a plurality of mapping unit pages and a mapping unit page directory; and

performing, with the data storage controller, one or more memory operations with the indexless L2PTT.

14. The method of claim 13 , wherein the one or more memory operations is a L2PTT update operation that includes

identifying a free slot in the mapping unit staging page,

copying a mapping unit page from the indexless L2PTT to the identified free slot in the mapping unit staging page, and

recording a mapping unit page index, associated with the copied mapping unit page, in the mapping unit page directory in the mapping unit staging page.

15. The method of claim 13 , wherein the one or more memory operations is a closed L2PTT flash block compaction operation includes

determining, with the data storage controller and a mapping unit page location index, a set of mapping unit pages, wherein each mapping unit page, included in the set of mapping unit pages, is valid, and

storing the each mapping unit page, included in the set of mapping unit pages, into the mapping unit staging page.

16. The method of claim 13 , wherein the one or more memory operations is a L2PTT initialization operation that includes performing a serial initialization operation.

17. The method of claim 16 , wherein the memory includes a list of flash blocks dedicated for L2PTT storage, wherein the data storage controller memory further includes a mapping unit page location index, and wherein the serial initialization operation includes

determining, using the mapping unit page directory, a set of mapping unit pages staged in the mapping unit staging page,

processing the mapping unit page directory, and

for each mapping unit page index included in the mapping unit page directory,

determine whether a record in the mapping unit page location index has been initialized,

when the record in the mapping unit page location index has not been initialized, initialize the record, in the mapping unit page location index, with a relative index of a corresponding flash block in the list of flash blocks dedicated for L2PTT storage, and

copy content of a mapping unit page from a location of the mapping unit page, in the mapping unit staging page, to a corresponding location in the indexless L2PTT.

18. The method of claim 13 , wherein the one or more memory operations is a L2PTT initialization operation that includes performing a parallel initialization operation.

19. The method of claim 18 , wherein the memory includes a list of flash blocks dedicated for L2PTT storage, wherein the data storage controller memory further includes a mapping unit page location index, and wherein the parallel initialization operation includes

determining, using the mapping unit page directory, a set of mapping unit pages staged in the mapping unit staging page,

processing the mapping unit page directory, and

for each mapping unit page index included in the mapping unit page directory,

determine whether a record in the mapping unit page location index has been initialized,

when the record in the mapping unit page location index has been initialized, compare i) a first flash block location of a mapping unit page being processed with ii) a second flash block location saved in an auxiliary data structure storing latest flash block locations of each mapping unit page, to determine whether the mapping unit page has been initialized,

when the mapping unit page has not been initialized,

initialize the record, in the mapping unit page location index, with a relative index of a corresponding flash block in the list of flash blocks dedicated for L2PTT storage, and

save, in the auxiliary data structure, the first flash block location of the mapping unit page being processed, and

copy content of the mapping unit page from a location of the mapping unit page, in the mapping unit staging page, to a corresponding location in the indexless L2PTT.

20. A non-transitory computer-readable medium comprising instructions that, when executed by an electronic processor, cause the electronic processor to perform a set of operations comprising:

generating an indexless logical-to-physical translation table (L2PTT) in a data storage controller memory of a data storage controller;

staging a mapping unit staging page, based on the indexless L2PTT, in a memory, the mapping unit staging page including a plurality of mapping unit pages and a mapping unit page directory; and

performing one or more memory operations with the indexless L2PTT.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2022
From: KRAGEL, OLEG; SIVASANKARAN, VIJAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060050/0660 →