IP Library Granted Patent US 8,521,967
Granted Patent B1
US 8,521,967 · App. 12/490,941 · Granted Aug 27, 2013

Network computing systems having shared memory clouds with addresses of disk-read-only memories mapped into processor address spaces

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,521,967
App. No.
12/490,941
Granted
Aug 27, 2013
Kind
B1
Abstract

Network computing systems are disclosed including a shared memory cloud coupled to one or more processor complexes. The shared memory cloud has an interconnect network coupled to disk-read-only-memories (disk-ROMs) each including a memory array that is read/write block accessible to access blocks of consecutive memory locations and random read memory accessible to access random memory locations. The processor complexes read and write blocks of data from/to the disk-ROMs to provide disk-like access to the shared memory cloud. Each processor complex maps the addresses of one or more of the disk-ROMs into processor address spaces, and reads from random memory locations of one or more of the disk-ROMs to provide main memory-like access to the shared memory cloud. The network computing systems may further include a power controller coupled to the processor complexes. The power controller can keep the disk-ROMS powered on while it powers off inactive processor complexes.

Claims (78)

1. A network computing system comprising:

a shared memory cloud including a plurality of disk-read-only-memories (disk-ROMs) coupled to an interconnect network suitable for memory read operations and block read/write operations, each of the disk-read-only-memories including a memory array that is read/write block accessible to access blocks of consecutive memory locations and random read memory accessible to access random memory locations;

one or more processor complexes coupled to the shared memory cloud, the one or more processor complexes to read blocks of data from and write blocks of data into consecutive memory locations of one or more of the plurality of disk-ROMS to provide disk-like access to the shared memory cloud; and

wherein each processor complex maps the addresses of one or more of the plurality of disk-read-only-memories into processor address spaces to provide memory read access thereto, the one or more processor complexes to read random locations of data from random memory locations of one or more of the plurality of disk-ROMS to provide main-memory-like access to the shared memory cloud.

2. The network computing system of claim 1 , wherein

a total memory space of the shared memory cloud provided by the plurality of disk-ROMs may be pooled together and mapped for usage by one of the one or more processor complexes.

3. The network computing system of claim 1 , wherein

a total memory space of the shared memory cloud provided by the plurality of disk-ROMs is partitioned into a plurality of memory space partitions, and

one or more of the memory space partitions are mapped for usage by one of the one or more processor complexes.

4. The network computing system of claim 1 , wherein

the interconnect network is a hypertransport (HT) routable point to point mesh network.

5. The network computing system of claim 1 , wherein

the interconnect network is a routable point to point packet-switched mesh network.

6. The network computing system of claim 1 , further comprising:

one or more packet routers coupled to the plurality of disk-read-only-memories (disk-ROMs) and the one or more processor complexes, each of the one or more packet routers to route read and write packets towards one of the disk-ROMs or processor complexes in response to a routing table and each destination address of the read and write packets.

7. The network computing system of claim 1 , wherein

one or more of the plurality of disk-read-only-memories (disk-ROMs) in the shared memory cloud include a packet router coupled to other disk-read-only-memories (disk-ROMs) and the one or more processor complexes, the packet router to route read and write packets towards one of the disk-ROMs or processor complexes in response to a routing table and each destination address of the read and write packets.

8. The network computing system of claim 1 , wherein

software drivers in each processor complex map the addresses of the one or more of the plurality of disk-read-only-memories into processor address spaces to provide memory read access thereto.

9. The network computing system of claim 1 , further comprising:

at least one power controller coupled to the one or more processor complexes; and

wherein the at least one power controller to keep the plurality of disk-ROMS powered on while it powers off one or more inactive processor complexes.

10. The network computing system of claim 9 , wherein

upon request, the at least one power controller to power back on one or more processor complexes to execute a process including one or more instructions.

11. The network computing system of claim 1 , wherein

software drivers in each processor complex initiate the block read/write accesses with the plurality of disk-ROM devices and cooperate with each other to coordinate accesses into each disk-ROM device to avoid disk-ROM resource contentions.

12. The network computing system of claim 11 , wherein

the software drivers cooperate with each other to invalidate a plurality of cache lines in respective cache memories of the one or more processor complexes in response to an accumulated plurality of memory change notifications to provide coherency of data in the plurality of disk ROM devices.

13. The network computing system of claim 1 , wherein

each of the disk-read-only-memories (disk-ROMs) in the shared memory cloud includes a packet router, each packet router to route read and write packets towards one of the disk-ROMs or processor complexes in response to a routing table and each destination address of the read and write packets.

14. The network computing system of claim 13 , wherein

each packet router to couple to one or more packet routers in other disk-ROMs.

15. The network computing system of claim 13 , wherein

each packet router to couple to the one or more processor complexes.

16. A network computing system comprising:

a shared memory cloud including a plurality of disk-read-only-memories (disk-ROMs) coupled to an interconnect network suitable for memory read operations and block read/write operations, each of the disk-ROMS including a memory array that is read/write block accessible to access blocks of consecutive memory locations and random read memory accessible to access random memory locations;

a plurality of processor complexes coupled to the shared memory cloud, the plurality of processor complexes to read blocks of data from and write blocks of data into consecutive memory locations of one or more of the plurality of disk-ROMS to provide disk-like access to the shared memory cloud, wherein each processor complex maps the addresses of one or more of the plurality of disk-read-only-memories into processor address spaces to provide memory read access thereto, the plurality of processor complexes to read random locations of data from random memory locations of one or more of the plurality of disk-ROMS to provide main-memory-like access to the shared memory cloud; and

wherein a total memory space of the shared memory cloud provided by the plurality of disk-ROMs is pooled together and mapped for usage by the plurality of processor complexes.

17. The network computing system of claim 16 , wherein

the interconnect network is a hypertransport (HT) routable point to point mesh network.

18. The network computing system of claim 16 , wherein

the interconnect network is a routable point to point packet-switched mesh network.

19. The network computing system of claim 16 , further comprising:

one or more packet routers coupled to the plurality of disk-read-only-memories (disk-ROMs) and the plurality of processor complexes, each of the one or more packet routers to route read and write packets towards one of the disk-ROMs or processor complexes in response to a routing table and each destination address of the read and write packets.

20. The network computing system of claim 16 , wherein

each of the plurality of processor complexes includes a software driver to map the addresses of the one or more of the plurality of disk-read-only-memories into processor address spaces to provide memory read access thereto.

21. The network computing system of claim 16 , wherein

each of the disk-read-only-memories (disk-ROMs) in the shared memory cloud includes a packet router, each packet router to route read and write packets towards one of the disk-ROMs or processor complexes in response to a routing table and each destination address of the read and write packets.

22. The network computing system of claim 21 , wherein

each packet router to couple to one or more packet routers in other disk-ROMs.

23. The network computing system of claim 22 , wherein

each packet router to couple to the plurality of processor complexes.

24. The network computing system of claim 16 , further comprising:

at least one power controller coupled to the plurality of processor complexes; and

wherein the at least one power controller to keep the plurality of disk-ROMS powered on while it powers off one or more inactive processor complexes.

25. The network computing system of claim 24 , wherein

upon request, the at least one power controller to power back on the plurality of processor complexes to execute a process including one or more instructions.

26. The network computing system of claim 16 , wherein

each of the plurality of processor complexes includes a software driver to initiate the block read/write accesses with the plurality of disk-ROM devices and to cooperate with each other to coordinate accesses into each disk-ROM device to avoid disk-ROM resource contentions.

27. The network computing system of claim 26 , wherein

the software drivers cooperate with each other to invalidate a plurality of cache lines in respective cache memories of the plurality of processor complexes in response to an accumulated plurality of memory change notifications to provide coherency of data in the plurality of disk ROM devices.

28. A network computing system comprising:

a shared memory cloud including a plurality of disk-read-only-memories (disk-ROMs) coupled to an interconnect network suitable for memory read operations and block read/write operations, each of the disk-ROMS including a memory array that is read/write block accessible to access blocks of consecutive memory locations and random read memory accessible to access random memory locations;

a plurality of processor complexes coupled to the shared memory cloud, the plurality of processor complexes to read blocks of data from and write blocks of data into consecutive memory locations of one or more of the plurality of disk-ROMS to provide disk-like access to the shared memory cloud, wherein each processor complex maps the addresses of one or more of the plurality of disk-read-only-memories into processor address spaces to provide memory read access thereto, the plurality of processor complexes to read random locations of data from random memory locations of one or more of the plurality of disk-ROMS to provide main-memory-like access to the shared memory cloud; and

wherein a total memory space of the shared memory cloud provided by the plurality of disk-ROMs is partitioned into a plurality of memory space partitions, and the plurality of memory space partitions are respectively mapped for usage by the plurality of processor complexes.

29. The network computing system of claim 28 , further comprising:

one or more packet routers coupled to the plurality of disk-read-only-memories (disk-ROMs) and the plurality of processor complexes, each of the one or more packet routers to route read and write packets towards one of the disk-ROMs or processor complexes in response to a routing table and each destination address of the read and write packets.

30. The network computing system of claim 29 , wherein

one or more of the plurality of disk-read-only-memories (disk-ROMs) in the shared memory cloud include a packet router coupled to other disk-read-only-memories (disk-ROMs) and the plurality of processor complexes, the packet router to route read and write packets towards one of the disk-ROMs or processor complexes in response to a routing table and each destination address of the read and write packets.

31. The network computing system of claim 29 , further comprising:

at least one power controller coupled to the plurality of processor complexes; and

wherein the at least one power controller to keep the plurality of disk-ROMS powered on while it powers off one or more inactive processor complexes.

32. The network computing system of claim 31 , wherein

upon request, the at least one power controller to power back on at least one of the one or more inactive processor complexes to execute a process including one or more instructions.

33. The network computing system of claim 28 , wherein

software drivers in each processor complex initiate the block read/write accesses with the plurality of disk-ROM devices and cooperate with each other to coordinate accesses into each disk-ROM device to avoid disk-ROM resource contentions.

34. The network computing system of claim 28 , wherein

software drivers in each processor complex map the addresses of the one or more of the plurality of disk-read-only-memories into processor address spaces to provide memory read access thereto.

Assignments (11)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2020
From: VIRIDENT SYSTEMS, LLC
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053180/0472 →
CHANGE OF NAME Recorded Jan 30, 2019
From: VIRIDENT SYSTEMS, INC
To: VIRIDENT SYSTEMS, LLC
Reel/Frame 048196/0580 →