IP Library Granted Patent US 10,637,533
Granted Patent B2
US 10,637,533 · App. 16/146,238 · Granted Apr 28, 2020

Dedicated termination dies for memory systems

Inventors: John Thomas Contreras (Palo Alto, CA); Sayed Mobin (Milpitas, CA); David Zhang (Milpitas, CA); Gokul Kumar (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
H04B3/54H01L25/0657H01L2225/06541
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Quick Facts
Patent No.
US 10,637,533
App. No.
16/146,238
Granted
Apr 28, 2020
Kind
B2
Abstract

An apparatus includes a controller die and a group of dies that communicate with each other via a transmission line. Less than all of the dies of the group includes a respective on-die termination resistance circuit coupled to the transmission line. In some embodiments, one of the dies that includes an on-die termination resistance circuit is an end die of the group. In particular embodiments, the end die is the only die of the group that includes an on-die termination resistance circuit coupled to the transmission line. Transmission frequencies or data rates may be increased without degrading signal quality by removing capacitance associated with on-die termination resistance circuits from at least one of the dies of the group.

Claims (35)

1. An apparatus comprising:

a transmission line; and

a group of dies coupled to the transmission line, wherein the group of dies comprises:

a first die configured with an on-die termination resistance circuit coupled to the transmission line, wherein the first die is not configured to store data; and

a second die configured without any on-die termination resistance circuits coupled to the transmission line.

2. The apparatus of claim 1 , wherein none of the other dies of the group, except the first die, comprises a respective on-die termination resistance circuit coupled to the transmission line.

3. The apparatus of claim 1 , wherein the first die comprises an end die of the group.

4. The apparatus of claim 1 , wherein the group of dies is coupled to the transmission line via a wire bond portion of the transmission line.

5. The apparatus of claim 1 , wherein the group of dies is configured as a die stack.

6. The apparatus of claim 5 , wherein the die stack comprises a staircase stack.

7. The apparatus of claim 1 , wherein the group of dies is configured to communicate over the transmission line at a predetermined high frequency and at a predetermined low frequency, and wherein the on-die termination resistance circuit is configured to:

set an associated resistance at a low level when the group of dies communicates over the transmission line at the predetermined high frequency; and

set the associated resistance at a high level when the group of dies communicates over the transmission line at the predetermined low frequency.

8. An apparatus comprising:

a controller die;

a group of dies configured to communicate with the controller die via a transmission line, wherein the group of dies comprises a plurality of memory dies and an end die that is not configured to store data,

wherein the end die comprises at least one on-die termination circuit coupled to the transmission line, and

wherein less than all of the group of dies comprises a respective one of the at least one on-die termination circuit.

9. The apparatus of claim 8 , wherein only one of the dies of the group comprises the at least one on-die termination circuit coupled to the transmission line.

10. The apparatus of claim 9 , wherein the only one of the dies comprises the end die.

11. The apparatus of claim 8 , wherein the end die is configured to perform error correction.

12. The apparatus of claim 8 , wherein the end die does not include additional circuitry other than input/output contact pads and on-die resistance circuits.

13. The apparatus of claim 8 , wherein the group of dies is coupled to the transmission line via a wire bond portion of the transmission line.

14. The apparatus of claim 8 , wherein the group of dies is configured as a die stack.

15. The apparatus of claim 14 , wherein the die stack comprises a staircase stack.

16. The apparatus of claim 8 , wherein the controller die and the group of dies are configured to communicate over the transmission line at a predetermined high frequency and at a predetermined low frequency, and wherein the at least one on-die termination resistance circuit is configured to:

set an associated resistance at a low level for communication over the transmission line at the predetermined high frequency; and

set the associated resistance at a high level for communication over the transmission line at the predetermined low frequency.

17. A method comprising:

setting an on-die termination resistance circuit of an end die of a group of dies to a low level, the on-die termination resistance circuit coupled to a transmission line, wherein no other dies of the group of dies comprises a respective on-die termination resistance circuit, and wherein the end die does not contain memory; and

communicating a signal over the transmission line between the group of dies and a controller die with the on-die termination resistance circuit set to the low level.

18. The method of claim 17 , wherein communicating the signal comprises communicating the signal at a predetermined high frequency, and wherein setting the on-die termination resistance circuit to the low level is dependent on communicating the signal at the predetermined high frequency.

19. The method of claim 17 , wherein the signal comprises a first signal, the method further comprises:

setting the on-die termination resistance circuit of the end die to a high level dependent on communicating a second signal over the transmission line at a predetermined low frequency; and

communicating the second signal over the transmission line between the group of dies and the controller die with the on-die termination resistance circuit set to the high level.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2019
From: CONTRERAS, JOHN THOMAS; MOBIN, SAYED; ZHANG, DAVID; KUMAR, GOKUL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 048061/0281 →