IP Library Granted Patent US 12,020,751
Granted Patent B2
US 12,020,751 · App. 17/714,379 · Granted Jun 25, 2024

Read threshold calibration for cross-temperature long, sequential reads

Inventors: Eran Sharon (Rishon Lezion, IL); Nika Yanuka (Hadera, IL); Idan Alrod (Herzeliya, IL); Alexander Bazarsky (Holon, IL); Evgeny Mekhanik (Rehovot, IL)
Assignee: Western Digital Technologies, Inc.
G11C16/102G11C7/04G11C16/08G11C16/24G11C16/26G11C2207/2254
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Quick Facts
Patent No.
US 12,020,751
App. No.
17/714,379
Granted
Jun 25, 2024
Kind
B2
Abstract

A system and method for calibrating read threshold voltages includes performing a plurality of read operations, determining to perform a read level tracking method, and performing the read level tracking method. The determining may be based on a temperature change or a bit error rate (BER). The read level tracking method includes determining the BER of an indicative word line, determining an adjusted read threshold level based on the BER, and adjusting read threshold levels according to the adjusted read threshold level.

Claims (47)

1. A method of calibrating read threshold voltages during a sequential read operation, the method comprising:

performing a plurality of sequential read operations;

determining, subsequent to a first read operation of a first word line (WL), whether to perform a read level tracking (RLT) operation based on a comparison between a bit error rate (BER) of the first WL and a predetermined threshold;

in response to a determination that the BER of the first WL is greater than the predetermined threshold, performing the RLT operation during a second read operation performed on a second WL;

determining an adjusted read threshold level based on results of the RLT operation performed during the second read operation on the second WL;

adjusting, for read operations performed subsequent to the second read operation, read threshold levels according to the adjusted read threshold level; and

performing at least one read operation subsequent to the second read operation according to the adjusted read threshold level.

2. The method according to claim 1 , wherein determining whether to perform the RLT operation further comprises determining whether the first WL is an outlier WL.

3. The method according to 2 , wherein the outlier WL is an edge WL.

4. The method according to claim 1 , wherein determining whether to perform the RLT operation comprises determining whether a temperature change with respect to a previous RLT operation is above a temperature threshold.

5. The method according to claim 1 , further comprising:

determining the BER by:

determining a plurality of voltage bins,

for each of the plurality of voltage bins, determining a corresponding BER; and

determining the adjusted read threshold level by:

for each of the plurality of voltage bins, calculating a Gaussian tail distribution function based on the corresponding BER, and

determining a distance of a read threshold from an optimal read threshold for each of the plurality of voltage bins.

6. The method according to claim 5 , wherein determining the plurality of voltage bins comprises, for each memory state resulting from the plurality of sequential read operations, determining a corresponding voltage bin.

7. The method according to claim 1 , wherein determining the BER comprises estimating the BER using a corresponding syndrome weight.

8. The method according to claim 1 , wherein performing the plurality of sequential read operations comprises performing the plurality of sequential read operations according to a host request.

9. The method according to claim 1 , wherein determining an adjusted read threshold level based on the results of the RLT operation comprises applying a WL zoning table.

10. A system for calibrating read threshold voltages during a sequential read operation, the system comprising a controller in operative communication with at least one memory die, the controller comprising:

an interface configured to receive, from the at least one memory die, a number of bits corresponding to a plurality of sequential read operations; and

a processor configured to:

determine, subsequent to a first read operation of a first word line (WL), whether to perform a read level tracking (RLT) operation based on a comparison between a bit error rate (BER) of the first WL and a predetermined threshold;

in response to a determination that the BER of the first WL is greater than the predetermined threshold, perform the RLT operation during a second read operation performed on a second WL;

determine an adjusted read threshold based on results of the RLT operation performed during the second read operation on the second WL;

adjust, for read operations performed subsequent to the second read operation, read threshold levels according to the adjusted read threshold level; and

perform at least one read operation subsequent to the second read operation according to the adjusted read threshold level.

11. The system according to claim 10 , wherein the processor is configured to determine whether to perform the RLT operation by determining whether the first WL is an outlier WL.

12. The system according to claim 11 , wherein the outlier WL is an edge WL.

13. The system according to claim 10 , wherein the processor is configured to determine whether perform the RLT operation by determining whether a temperature change with respect to a previous RLT method is above a temperature threshold.

14. The system according to claim 10 , wherein:

to determine the BER, the processor is configured to:

determine a plurality of voltage bins,

for each of the plurality of voltage bins, determine a corresponding BER; and

to determine the adjusted read threshold level, the processor is configured to:

for each of the plurality of voltage bins, calculate a Gaussian tail distribution function based on the corresponding BER, and

determine a distance of a read threshold from an optimal read threshold for each of the plurality of voltage bins.

15. A system for calibrating read threshold values during a sequential read operation, the system comprising a control means in operative communication with at least one memory die, the control means comprising:

an interface means configured to receive, from the at least one memory die, a number of bits corresponding to a plurality of sequential read operations; and

processing means configured to:

determine, subsequent to a first read operation of a first word line (WL), whether to perform a read level tracking (RLT) operation based on a comparison between a bit error rate (BER) of the first WL and a predetermined threshold;

in response to a determination that the BER of the first WL is greater than the predetermined threshold, perform the RLT operation during a second read operation performed on a second WL;

determine an adjusted read threshold based on results of the RLT operation performed during the second read operation on the second WL;

adjust, for read operations performed subsequent to the second read operation, read threshold levels according to the adjusted read threshold level; and

perform at least one read operation subsequent to the second read operation using the adjusted read threshold level.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2022
From: SHARON, ERAN; YANUKA, NIKA; ALROD, IDAN; BAZARSKY, ALEXANDER; MEKHANIK, EVGENY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059764/0800 →
Continuity (1)
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