Methods and systems for memory page allocation
View Patent ↗Techniques for improving memory page allocation are disclosed. In some embodiments, the techniques may be realized as a method for improving memory page allocation including generating, using a compression unit, compressed grains associated with compressed blocks, identifying a write page allocation unit to query, receiving, at the write page allocation unit, a query for a flash memory location to store the compressed grains, determining a flash memory location for the compressed grains, determining a parity location for the compressed grains, returning offsets indicating the flash memory location and the parity location, sending the compressed grains to the free grain location and a parity bit to the parity location as part of an atomic transaction, and recording a start location of compressed grains in a mapping.
1. A method for improving memory page allocation comprising:
generating, using a compression unit, compressed grains associated with compressed blocks;
identifying a write page allocation unit to query;
receiving, at the write page allocation unit, a query for a flash memory location to store the compressed grains, wherein the query includes an indicator of the compression unit;
determining a flash memory location for the compressed grains, wherein the flash memory location is a free grain location;
determining a parity location for the compressed grains;
returning offsets indicating the flash memory location and the parity location to the compression unit based on the indicator of the compression unit;
sending, the compressed grains to the free grain location and a parity bit to the parity location as part of an atomic transaction; and
recording a start location of compressed grains in a mapping.
2. The method of claim 1 , wherein the compression unit identifies the write page allocation unit to query.
3. The method of claim 1 , wherein the write page allocation unit is identified based at least in part on a type of block currently being compressed by the compression unit.
4. The method of claim 3 , wherein the type of block includes at least one of: a block associated with host traffic, a block associated with Solid State Device (SSD) controller administrative traffic, and a block associated with storage infrastructure traffic.
5. The method of claim 1 wherein the determined flash memory location for the compressed grains comprises a flash memory channel SRAM buffer location.
6. The method of claim 1 , comprising calculating the parity bit for the compressed grains using an XOR parity scheme.
7. The method of claim 1 , wherein determining a parity location for the compressed grains comprises identifying a flash memory channel SRAM buffer location.
8. The method of claim 1 , wherein determining the flash memory location for the compressed grains comprises identifying a flash memory line.
9. The method of claim 8 , wherein determining the flash memory location for the compressed grains comprises identifying a memory die of the identified flash memory line.
10. The method of claim 1 , wherein determining the flash memory location for the compressed grains comprises at least one of tracking free grains in flash memory and tracking unavailable flash memory.
11. The method of claim 1 , wherein determining a parity location for the compressed grains comprises aligning one or more parity blocks at an end of a flash page associated with the compressed grains.
12. A non-transient computer readable medium containing program instructions executable on a computer, for causing the computer to perform a process for improving memory page allocation comprising:
generating, using a compression unit, compressed grains associated with compressed blocks;
identifying a write page allocation unit to query;
receiving, at the write page allocation unit, a query for a flash memory location to store the compressed grains, wherein the query includes an indicator of the compression unit;
determining a flash memory location for the compressed grains, wherein the flash memory location is a free grain location;
determining a parity location for the compressed grains;
returning offsets indicating the flash memory location and the parity location to the compression unit based on the indicator of the compression unit;
sending the compressed grains to the free grain location and a parity bit to the parity location as part of an atomic transaction; and
recording a start location of compressed grains in a mapping.
13. A system for improving memory page allocation, the system comprising:
a storage media device;
a PCIe-based device controller associated with the storage media device, wherein the PCIe-based device controller is configured to:
generate, using a compression unit, compressed grains associated with compressed blocks;
identify a write page allocation unit to query;
receive, at the write page allocation unit, a query for a flash memory location to store the compressed grains, wherein the query includes an indicator of the compression unit;
determine a flash memory location for the compressed grains, wherein the flash memory location is a free grain location;
determine a parity location for the compressed grains;
return offsets indicating the flash memory location and the parity location to the compression unit based on the indicator of the compression unit;
send the compressed grains to the free grain location and a parity bit to the parity location as part of an atomic transaction; and
record a start location of compressed grains in a mapping.
14. The system of claim 13 , wherein the compression unit identifies the write page allocation unit to query.
15. The system of claim 13 , wherein the write page allocation unit is identified based at least in part on a type of block currently being compressed by the compression unit.
16. The system of claim 15 , wherein the type of block includes at least one of: a block associated with host traffic, a block associated with Solid State Device (SSD) controller administrative traffic, and infrastructure traffic.
17. The system of claim 13 , wherein the determined flash memory location for the compressed grains comprises a flash memory channel SRAM buffer location.
18. The system of claim 13 , further comprising calculating the parity bit for the compressed grains using an XOR parity scheme.
19. The system of claim 13 , wherein determining a parity location for the compressed grains comprises identifying a flash memory channel SRAM buffer location.
20. The system of claim 13 , wherein determining the flash memory location for the compressed grains comprises identifying a flash memory line.
21. The system of claim 20 , wherein determining the flash memory location for the compressed grains comprises identifying a memory die of the identified flash memory line.
22. The system of claim 13 , wherein determining a parity location for the compressed grains comprises aligning one or more parity blocks at an end of a flash page associated with the compressed grains.