IP Library Granted Patent US 8,677,035
Granted Patent B2
US 8,677,035 · App. 13/754,837 · Granted Mar 18, 2014

Data storage system with primary and secondary compression engines

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Quick Facts
Patent No.
US 8,677,035
App. No.
13/754,837
Granted
Mar 18, 2014
Kind
B2
Abstract

Aspects of the subject technology relate to a data storage system controller including a host interface configured to be coupled to a host device, to receive data from the host device, and to send data to the host device. In certain aspects, the data storage system includes a primary compression engine configured to compress data received from the host device via the host interface, and a secondary compression engine configured to decompress and compress data associated with operations internal to the data storage system. In some implementations, the data storage systems can further include a processor configured to transfer data between the host interface and the primary compression engine, between the primary compression engine and a non-volatile storage medium, between a memory and the secondary compression engine, and between the secondary compression engine and the memory. A data storage system is also provided.

Claims (60)

1. A data storage system comprising:

a host interface configured to be coupled to a host device, to receive data from the host device, and to send data to the host device;

a memory coupled to a bus;

a primary compression engine comprising:

a compression input buffer coupled to the host interface;

a primary compression engine core coupled to the compression input buffer; and

a compression output buffer coupled to the primary compression engine core and the bus,

wherein the primary compression engine core is configured to compress data in the compression input buffer received from the host device via the host interface and to store the compressed data in the compression output buffer;

a secondary compression engine comprising:

a secondary input buffer coupled to the bus;

a secondary compression engine core coupled to the secondary input buffer; and

a secondary output buffer coupled to the secondary compression engine core and the bus,

wherein the secondary compression engine core is configured to compress data in the secondary input buffer and store the compressed data in the secondary output buffer, and to decompress data in the secondary input buffer and store the decompressed data in the secondary output buffer;

a non-volatile storage medium coupled to the bus; and

a processor coupled to the bus and configured to transfer data between the host interface and the compression input buffer, between the compression output buffer and the non-volatile storage medium, between the memory and the secondary input buffer, and between the secondary output buffer and the memory,

wherein the data compression and decompression performed by the secondary compression engine is associated with operations internal to the data storage system.

2. The data storage system of claim 1 , wherein the operations comprise read-modify-write operations used to manage data stored in the non-volatile storage medium.

3. The data storage system of claim 1 , wherein the primary compression engine core is configured to compress a logical unit of data in the compression input buffer and to stop compressing the logical unit of data if an amount of compressed data generated from the logical unit of data exceeds a threshold.

4. The data storage system of claim 3 , wherein the compression input buffer is coupled to the bus, and wherein the processor is further configured to transfer the logical unit of data from the compression input buffer to the non-volatile storage medium if compression of the logical unit of data is stopped by the primary compression engine core.

5. The data storage system of claim 1 , wherein the primary compression engine has a higher data throughput than the secondary compression engine.

6. The data storage system of claim 1 , wherein the primary compression engine further comprises a compression bypass buffer coupled to the host interface and the bus,

wherein the processor is further configured to transfer data between the host interface and the compression bypass buffer and between the compression bypass buffer and the non-volatile storage medium without passing the data through the primary compression engine core.

7. The data storage system of claim 1 , wherein the primary compression engine further comprises:

a decompression input buffer coupled to the bus;

a decompression engine core coupled to the decompression input buffer; and

a decompression output buffer coupled to the decompression engine core and the host interface,

wherein the decompression engine core is configured to decompress data in the decompression input buffer and store the decompressed data in the decompression output buffer, and

wherein the processor is further configured to transfer data between the non-volatile storage medium and the decompression input buffer and between the decompression output buffer and the host interface.

8. The data storage system of claim 7 , wherein the primary compression engine further comprises a decompression bypass buffer coupled to the bus and the host interface,

wherein the process is further configured to transfer data between the non-volatile storage medium and the decompression bypass buffer and between the decompression bypass buff and the host interface without passing the data through the decompression engine core.

9. The data storage system of claim 1 , wherein the non-volatile storage medium comprises flash memory.

10. A data storage system controller comprising:

a host interface configured to be coupled to a host device, to receive data from the host device, and to send data to the host device;

a primary compression engine configured to compress data received from the host device via the host interface;

a secondary compression engine configured to decompress and compress data associated with operations internal to the data storage system; and

a processor configured to transfer data between the host interface and the primary compression engine, between the primary compression engine and a non-volatile storage medium, between a memory and the secondary compression engine, and between the secondary compression engine and the memory,

wherein the secondary compression engine is configured to decompress and compress only data received from the memory.

11. The data storage system controller of claim 10 , wherein the operations comprise read-modify-write operations used to manage data stored in the non-volatile storage medium.

12. The data storage system controller of claim 10 , wherein the primary compression engine comprises:

a compression input buffer coupled to the host interface;

a primary compression engine core coupled to the compression input buffer; and

a compression output buffer coupled to the primary compression engine core and the bus,

wherein the primary compression engine core is configured to compress data in the compression input buffer received from the host device via the host interface and to store the compressed data in the compression output buffer.

13. The data storage system controller of claim 12 , wherein the secondary compression engine comprises:

a secondary input buffer coupled to the bus;

a secondary compression engine core coupled to the secondary input buffer; and

a secondary output buffer coupled to the secondary compression engine core and the bus,

wherein the secondary compression engine core is configured to compress data in the secondary input buffer and store the compressed data in the secondary output buffer, and to decompress data in the secondary input buffer and store the decompressed data in the secondary output buffer.

14. The data storage system controller of claim 13 , wherein the primary compression engine core is configured to compress a logical unit of data in the compression input buffer and to stop compressing the logical unit of data if an amount of compressed data generated from the logical unit of data exceeds a threshold.

15. The data storage system controller of claim 14 , wherein the compression input buffer is coupled to the bus, and wherein the processor is further configured to transfer the logical unit of data from the compression input buffer to the non-volatile storage medium if compression of the logical unit of data is stopped by the primary compression engine core.

16. The data storage system controller of claim 13 , wherein the primary compression engine has a higher data throughput than the secondary compression engine.

17. The data storage system controller of claim 13 , wherein the primary compression engine further comprises a compression bypass buffer coupled to the host interface and the bus,

wherein the processor is further configured to transfer data between the host interface and the compression bypass buffer and between the compression bypass buffer and the non-volatile storage medium without passing the data through the primary compression engine core.

18. The data storage system controller of claim 13 , wherein the primary compression engine further comprises:

a decompression input buffer coupled to the bus;

a decompression engine core coupled to the decompression input buffer; and

a decompression output buffer coupled to the decompression engine core and the host interface,

wherein the decompression engine core is configured to decompress data in the decompression input buffer and store the decompressed data in the decompression output buffer, and

wherein the processor is further configured to transfer data between the non-volatile storage medium and the decompression input buffer and between the decompression output buffer and the host interface.

19. The data storage system controller of claim 13 , wherein the primary compression engine further comprises a decompression bypass buffer coupled to the bus and the host interface, wherein the process is further configured to transfer data between the non-volatile storage medium and the decompression bypass buffer and between the decompression bypass buffer and the host interface without passing the data through the decompression engine core.

Assignments (12)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2018
From: HGST TECHNOLOGIES SANTA ANA, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046174/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2016
From: LU, GUANGMING; MOSHAYEDI, MARK
To: STEC, INC.
Reel/Frame 039491/0292 →
CHANGE OF NAME Recorded Jul 1, 2015
From: STEC, INC.
To: HGST TECHNOLOGIES SANTA ANA, INC.
Reel/Frame 036042/0390 →