Granted Patent B2

US 9,208,871 · App. 13/361,918 · Granted Dec 8, 2015

Abstract

Claims (35)

1. A method for implementing data read for multi-level cell (MLC) memory comprising:

maintaining separate data identifying a current baseline voltage level on predefined MLC reference memory cells;

updating the separate data upon performing a partial-erase operation;

performing a data read back for data written to the MLC memory using an identified baseline voltage level;

comparing higher voltage and lower voltage levels; and

identifying respective data values responsive to the compared higher voltage and lower voltage levels.

2. The method for implementing data read as recited in claim 1 wherein maintaining separate data identifying the current baseline voltage level includes updating the separate data upon periodic data writes and full-erase.

3. The method for implementing data read as recited in claim 2 wherein identifying the current voltage baseline includes maintaining predefined parameter information on MLC memory cells; said predefined parameter information including said current voltage baseline.

4. The method for implementing data read as recited in claim 1 wherein maintaining separate data identifying the current baseline voltage level includes identifying actual reference voltage levels by read back from periodic reference cell writes on said predefined MLC reference memory cells.

5. The method for implementing data read as recited in claim 1 includes performing error recovery subroutine using said separate data identifying said current baseline voltage level.

6. The method for implementing data read as recited in claim 5 includes identifying said current baseline voltage level from periodic read back of reference voltage levels from predefined MLC reference memory cells.

7. The method for implementing data read as recited in claim 1 wherein maintaining separate data identifying the current baseline voltage level includes providing read criteria update using reference memory cell information for predefined MLC reference memory cells.

8. The method for implementing data read as recited in claim 7 wherein providing read criteria update includes using a number of write cycles and a number of erase cycles to determine voltage drift.

9. The method for implementing data read as recited in claim 7 wherein providing read criteria update includes writing the predefined MLC reference memory cells and separately storing write event conditions; and performing periodic read back of the predefined MLC reference memory cells to determine voltage drift.

10. The method for implementing data read as recited in claim 7 wherein providing read criteria update includes performing periodic read back of the predefined MLC reference memory cells, and using separately stored write event conditions including a baseline voltage level to determine voltage drift.

11. An apparatus for implementing data read for multi-level cell (MLC) memory comprising:

a controller;

said controller maintaining separate data identifying a current baseline voltage level on predefined MLC reference memory cells including said controller updating the separate data upon periodic data writes and full-erase;

said controller performing a data read back for data written to the MLC memory using an identified baseline voltage level;

said controller comparing higher voltage and lower voltage levels; and

said controller identifying respective data values responsive to the compared higher voltage and lower voltage levels.

12. The apparatus as recited in claim 11 includes control code stored on a non-transitory computer readable medium, and wherein said controller uses said control code for implementing data read back.

13. The apparatus as recited in claim 11 wherein said controller performing the data read back for data written to the MLC memory using an identified baseline voltage level includes said controller using said maintained separate data identifying the current baseline voltage level.

14. The apparatus as recited in claim 11 wherein said controller maintaining separate data identifying the current baseline voltage level includes said controller maintaining predefined parameter information on MLC memory cells; said predefined parameter information including the current baseline voltage level.

15. The apparatus as recited in claim 11 includes said controller performing error recovery subroutine using said separate data identifying the current baseline voltage level.

16. The apparatus as recited in claim 11 wherein said controller maintaining separate data identifying the current baseline voltage level includes said controller providing read criteria update using reference memory cell information for predefined MLC reference memory cells.

17. A data storage device comprising:

a multi-level cell (MLC) memory;

a controller for implementing data read;

said controller maintaining separate data identifying a current baseline voltage level on predefined MLC reference memory cell including said controller updating the separate data upon periodic data writes and full-erase; said controller identifying actual reference voltage levels by read back from periodic reference cell writes on said predefined MLC reference memory cells;

said controller performing a data read back for data written to the MLC memory using an identified baseline voltage level;

said controller comparing higher voltage and lower voltage levels; and

said controller identifying respective data values responsive to the compared higher voltage and lower voltage levels.

18. The data storage device as recited in claim 17 , wherein said controller maintaining separate data identifying the current voltage baseline includes said controller maintaining predefined parameter information including a voltage baseline.

19. The data storage device as recited in claim 17 , includes said controller performing error recovery subroutine using said separate data identifying the current baseline voltage level.

Assignments (12)