IP Library Granted Patent US 11,822,820
Granted Patent B2
US 11,822,820 · App. 17/523,124 · Granted Nov 21, 2023

Storage system and method for multi-cell mapping

Inventors: Ran Zamir (Ramat Gan, IL); Eran Sharon (Rishon Lezion, IL); Idan Alrod (Herzeliya, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/0604G06F3/0679G06F13/1668G11C11/5621G11C11/5628H04L27/36G11C2211/562
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Quick Facts
Patent No.
US 11,822,820
App. No.
17/523,124
Granted
Nov 21, 2023
Kind
B2
Abstract

A storage system has a memory with memory cells that can store a non-power-of-two number of states. A map is used to distribute data bits in the memory. The map can be a modified version of a quadrature amplitude modulation (QAM) map. The mapping can be done by a controller in the storage system or by the memory die. Performing the mapping in the memory die can reduce data traffic between the controller and the memory die, which can provide an improvement to performance and power consumption.

Claims (33)

1. A storage system for multi-cell mapping comprising:

a memory die comprising a plurality of memory cells, each memory cell configured to store a non-power-of-two number of states of voltage levels; and

a controller configured to provide data to the memory die for storage;

wherein the memory die is configured to:

map the data to the plurality of memory cells with a non-power-of-two number of voltage levels using a modified quadrature amplitude modulation (QAM) map; and

write the data into the plurality of memory cells as determined by the modified QAM map,

wherein the modified QAM map is created by:

reflecting a right and left half of a basic QAM map smaller than the modified QAM map on a right and an upper edge of the basic QAM map, respectively, and

moving a symbol in a right end of a portion reflected on the right edge and a symbol in an upper end of a portion reflected on the upper edge to an upper right of the basic QAM map.

2. The storage system of claim 1 , wherein the data is written into adjacent memory cells.

3. The storage system of claim 1 , further comprising performing state shaping to the modified QAM map.

4. The storage system of claim 1 , wherein the mapping is performed by a control die bonded to the memory die.

5. The storage system of claim 1 , wherein the non-power-of-two number is 23.

6. The storage system of claim 1 , wherein the memory die comprises a three-dimensional memory.

7. In a storage system with a memory die comprising a plurality of memory cells, each memory cell configured to store a non-power-of-two number of states of voltage levels, a method comprising:

mapping to the plurality of memory cells with a non-power-of-two number of voltage levels using a modified quadrature amplitude modulation (QAM) map; and

writing the data into the plurality of memory cells as determined by the modified QAM map,

wherein the modified QAM map is created by:

reflecting a right and left half of a basic QAM map smaller than the modified QAM map on a right and an upper edge of the basic QAM map, respectively, and

moving a symbol in a right end of a portion reflected on the right edge and a symbol in an upper end of a portion reflected on the upper edge to an upper right of the basic QAM map.

8. The method of claim 7 , wherein the data is written into adjacent memory cells.

9. The method of claim 7 , further comprising performing state shaping to the modified QAM map.

10. The method of claim 7 , wherein the mapping is performed by one of the following: a controller of the storage system, the memory die, or a control die bonded to the memory die.

11. The method of claim 7 , further comprising performing a de-mapping operation.

12. The method of claim 11 , wherein the de-mapping operation is performed by one of the following: a controller of the storage system, the memory die, or a control die bonded to the memory die.

13. The method of claim 7 , wherein the non-power-of-two number is 23.

14. A storage system comprising:

a memory die comprising a plurality of memory cells, each memory cell configured to store a non-power-of-two number of states of voltage levels;

means for mapping to the plurality of memory cells with a non-power-of-two number of voltage levels using a modified quadrature amplitude modulation (QAM) map; and

means for writing the data into the plurality of memory cells as determined by the modified QAM map,

wherein the modified QAM map is created by:

reflecting a right and left half of a basic QAM map smaller than the modified QAM map on a right and an upper edge of the basic QAM map, respectively, and

moving a symbol in a right end of a portion reflected on the right edge and a symbol in an upper end of a portion reflected on the upper edge to an upper right of the basic QAM map.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2021
From: ZAMIR, RAN; SHARON, ERAN; ALROD, IDAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058071/0776 →