IP Library Granted Patent US 11,281,405
Granted Patent B2
US 11,281,405 · App. 16/896,029 · Granted Mar 22, 2022

Controlled die asymmetry during MLC operations for optimal system pipeline

Inventors: Amit Sharma (Karnataka, IN); Abhinandan Venugopal (Karnataka, IN); Dinesh Kumar Agarwal (Karnataka, IN)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/0659G06F3/0613G06F3/0679G11C11/5628G11C11/5671G11C16/0483G11C16/10G11C16/26G11C2211/5641
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Quick Facts
Patent No.
US 11,281,405
App. No.
16/896,029
Granted
Mar 22, 2022
Kind
B2
Abstract

Aspects of a storage device including a plurality of dies and a controller are provided which allow for asymmetric die operation handling so that controller overheads associated with common resource intensive operations may be incurred in the background without delaying subsequent die operations. When the controller receives a command to perform an MLC operation such as programming a number of dies, the controller refrains from performing the MLC operation in one or more of the dies for a period of time while simultaneously performing the MLC operation in a remainder of the dies. Instead, the controller performs another operation, such as an SLC operation, another MLC operation, or a transfer operation, that involves a common resource in these dies during the period of time. Controller overheads associated with these other operations thus are incurred without creating bottlenecks when the number of dies is large, thereby improving storage device performance.

Claims (27)

1. A storage device, comprising:

a plurality of dies each including a plurality of multi-level cells (MLCs) and a plurality of single-level cells (SLCs); and

a controller configured to refrain from programming data in the MLCs of a number of the dies for a period of time while simultaneously programming one or more of the MLCs in each of a remainder of the dies, and to perform an SLC operation in the number of the dies during the period of time, wherein the number of the dies is based on a length of the period of time and a controller overhead associated with performing the SLC operation.

2. The storage device of claim 1 , wherein the SLC operation comprises one of a read operation or a write operation.

3. The storage device of claim 1 , wherein the MLCs each comprise one of a triple-level cell (TLC), a quadruple-level cell (QLC), or a penta-level cell (PLC).

4. The storage device of claim 1 , wherein the controller is further configured to program the data in one or more of the MLCs of the number of the dies after performing the SLC operation.

5. The storage device of claim 4 , wherein the controller is further configured to suspend programming the data in the one or more of the MLCs of the number of the dies while performing another SLC operation during a suspend resume window, and to resume the programming of the data during the suspend resume window after performing the another SLC operation.

6. The storage device of claim 1 , wherein the controller is further configured to refrain from programming the data in the MLCs of another one of the dies for another period of time while simultaneously programming one or more of the MLCs in each of another remainder of the dies, and to perform another SLC operation in the another one of the dies during the another period of time.

7. The storage device of claim 1 ,

wherein the controller is further configured to refrain from programming the data in the MLCs of additional ones of the dies for another period of time while simultaneously programming one or more of the MLCs in each of another remainder of the dies, and to perform other SLC operations in the additional ones of the dies during the another period of time.

8. A storage device, comprising:

a plurality of dies each including a plurality of multi-level cells (MLCs) and a plurality of single-level cells (SLCs); and

a controller configured to refrain from performing a first MLC operation in a number of the dies for a period of time while simultaneously performing the first MLC operation in one or more of the MLCs in each of a remainder of the dies, and to perform one of an SLC operation, a second MLC operation different than the first MLC operation, or a transfer operation in the number of the dies during the period of time, wherein the number of the dies is based on a length of the period of time and a controller overhead associated with performing the one of the SLC operation, the second MLC operation, or the transfer operation.

9. The storage device of claim 8 , wherein the SLC operation comprises one of a read operation or a write operation.

10. The storage device of claim 8 , wherein the controller includes a volatile memory having a buffer, and wherein the controller is configured during the second MLC operation to read data from the number of the dies into the buffer.

11. The storage device of claim 8 , wherein the controller is configured during the transfer operation to receive data from the number of the dies or to transmit data to the number of the dies.

12. The storage device of claim 8 , wherein the MLCs each comprise one of a triple-level cell (TLC), a quadruple-level cell (QLC), or a penta-level cell (PLC).

13. The storage device of claim 8 , wherein the controller is further configured to perform the first MLC operation in the number of the dies after performing the one of the SLC operation, the second MLC operation, or the transfer operation.

14. The storage device of claim 13 , wherein the controller is further configured to suspend performing the first MLC operation in the number of the dies while performing another SLC operation during a suspend resume window, and to resume performing the first MLC operation in the number of the dies during the suspend resume window after performing the another SLC operation.

15. The storage device of claim 8 , wherein the controller is further configured to refrain from performing another MLC operation in another one of the dies for another period of time while simultaneously performing the another MLC operation in one or more of the MLCs in each of another remainder of the dies, and to perform another SLC operation in the another one of the dies during the another period of time.

16. The storage device of claim 8 ,

wherein the controller is further configured to refrain from performing additional MLC operations in additional ones of the dies for another period of time while simultaneously performing the additional MLC operations in one or more of the MLCs in each of another remainder of the dies, and to perform other SLC operations in the additional ones of the dies during the another period of time.

17. A storage device, comprising:

a plurality of dies each including a plurality of multi-level cells (MLCs) and a plurality of single-level cells (SLCs); and

a controller configured to receive an MLC program command, to refrain from programming data in the MLCs of a number of the dies for a period of time while simultaneously programming one or more of the MLCs in each of a remainder of the dies, and to perform one of an SLC operation, a different MLC operation, or a transfer operation in the number of the dies during the period of time, wherein the number of the dies is based on a length of the period of time and a controller overhead associated with performing the one of the SLC operation, the different MLC operation, or the transfer operation.

18. The storage device of claim 17 , wherein the controller is further configured to program the data in one or more of the MLCs of the number of the dies after performing the one of the SLC operation, the different MLC operation, or the transfer operation in the number of the dies.

19. The storage device of claim 18 , wherein the controller is further configured to suspend programming the data in the one or more of the MLCs of the number of the dies while performing another SLC operation during a suspend resume window, and to resume the programming of the data during the suspend resume window after performing the another SLC operation.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2020
From: SHARMA, AMIT; VENUGOPAL, ABHINANDAN; AGARWAL, DINESH KUMAR
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053012/0139 →