Method and system for improving performance of a storage device using asynchronous independent plane read functionality
In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.
1. A method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprising:
receiving a request to perform an initial operation on a memory portion;
determining an operational characteristic associated with the initial operation to be performed on the memory portion; and
calculating an amount of time for a memory portion timer based on the operational characteristic at initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.
2. The method of claim 1 , wherein the operational characteristic includes at least one of: a memory characteristic, a page combination characteristic, and a sensing characteristic.
3. The method of claim 1 , wherein the operational characteristic is a memory characteristic that includes at least one of: program/erase cycle, data retention, cross-temperature, system temperature and read-disturb.
4. The method of claim 1 , wherein the operational characteristic is a page combination characteristic that includes at least one of: a single level cell page, multi-level cell (MLC) lower page, MLC middle page, and MLC upper page.
5. The method of claim 1 , wherein the operational characteristic is a sensing characteristic that includes at least one of: first read, normal read, Vreak spike and data look ahead.
6. The method of claim 1 , wherein a first time period for the performance of the initial operation on the memory portion overlaps with a second time period for the performance of a subsequent operation for another memory portion.
7. The method of claim 1 , wherein the memory portion is at least one of: a plane, a die, a block, a page.
8. A memory controller for performing implementing independent memory portion read operations on one or more memory portions for storing data, the memory controller configured to perform the operations of:
receiving a request to perform a first operation on a first memory portion;
determining, for a second memory portion, whether a second memory portion timer having a respective amount of time has elapsed since initiation of a second operation being performed on the second memory portion, separate and distinct from the first memory portion;
in response to a determination that the respective amount of time for the second memory portion timer has not elapsed:
delay performing the first operation on the first memory portion until the respective amount of time associated with initiation of the second operation performed on the second memory portion has elapsed, and
after delaying performance, performing the first operation on the first memory portion while the second operation continues to be performed on the second memory portion; and
in response to a determination that the respective amount of time for the second memory portion timer has elapsed, performing the first operation on the first memory portion.
9. The memory controller of claim 8 , wherein the memory controller is further configured to perform the operation of:
before performing the second operation on the second memory portion:
determining a respective operational characteristic of the second operation to be performed on the second memory portion; and
calculating the respective amount of time for the second memory portion timer based on the respective operational characteristic of the second operation to be performed on the second memory portion.
10. The memory controller of claim 9 , wherein the respective operational characteristic of the second operation is at least one of: memory characteristics, page combination characteristics and sensing operation characteristics of the respective memory portion.
11. The memory controller of claim 8 , wherein the memory controller is further configured to perform the operation of:
in response to performance of the first operation on the first memory portion, initializing a first memory portion timer including a respective amount of time to perform the first operation on the first memory portion.
12. The memory controller of claim 8 , wherein the first memory portion and the second memory portion are connected to a same power source.
13. The memory controller of claim 8 , wherein the first memory portion and the second memory portion are at least one of: a plane, a die, a block, and a page.