IP Library Granted Patent US 12,437,814
Granted Patent B2
US 12,437,814 · App. 18/242,061 · Granted Oct 7, 2025

Data storage device and method for predicting future read thresholds

Inventors: David Avraham (San Jose, CA); Alexander Bazarsky (Holon, IL); Eran Sharon (Rishon Lezion, IL); Ariel Navon (Revava, IL)
Assignee: Sandisk Technologies, Inc.
G11C16/26G11C16/3418G11C16/349
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Quick Facts
Patent No.
US 12,437,814
App. No.
18/242,061
Granted
Oct 7, 2025
Kind
B2
Abstract

Before a read threshold is needed to read a wordline in memory, a data storage device can infer a plurality of read thresholds based on possible conditions of the memory that may exist when the read threshold is eventually needed. When the read threshold is needed, it is selected from the previously-inferred read thresholds based on the current conditions of the memory. This can improve latency and throughput, improve quality of service, reduce power consumption, and reduce errors.

Claims (39)

1. A data storage device comprising:

a memory; and

a processor coupled with the memory and configured to:

before receiving a command to read a wordline in the memory, infer a plurality of read thresholds from a respective plurality of sets of parameter values and conditions of the memory that may exist when the command to read the wordline in the memory is received; and

in response to receiving the command to read the wordline in the memory:

determine a present set of parameter values and conditions of the memory; and

select a read threshold from the plurality of read thresholds based on the present set of parameter values and conditions of the memory.

2. The data storage device of claim 1 , wherein the processor is further configured to infer the plurality of read thresholds during an idle time.

3. The data storage device of claim 1 , wherein the processor is further configured to infer the plurality of read thresholds in parallel with a memory operation.

4. The data storage device of claim 1 , wherein the processor is further configured to infer the plurality of read thresholds using an inference engine with a large machine-learning model.

5. The data storage device of claim 4 , wherein the inference engine is implemented as firmware in a controller that comprises the processor.

6. The data storage device of claim 1 , wherein at least one parameter value in the plurality of sets of parameter values is fixed when inferring the plurality of read thresholds.

7. The data storage device of claim 6 , wherein the at least one parameter value comprises program temperature.

8. The data storage device of claim 6 , wherein the at least one parameter value comprises wordline number.

9. The data storage device of claim 1 , wherein the parameter values of the memory comprise: program/read temperature, program-erase-cycle count, and/or failed bit count.

10. The data storage device of claim 1 , wherein the parameter values of the memory comprise time and temperature group information, temperature information, bit error rate information, program-erase count (PEC) information, physical page location information, a read threshold on a representative wordline, a data retention level of a block, and/or a state-by-state cell-voltage-distribution measurement.

11. The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.

12. In a data storage device comprising a memory, a method comprising:

generating a plurality of inference exploration grids;

selecting an inference exploration grid from the plurality of inference exploration grids;

inferring a plurality of read thresholds from the selected inference exploration grid based on a plurality of possible memory conditions; and

prior to reading a wordline in the memory, selecting a set of read thresholds from the plurality of read thresholds based on a current memory condition.

13. The method of claim 12 , wherein the generating the plurality of inference exploration grids is scheduled after a time and temperature group information update is conducted.

14. The method of claim 12 , wherein a plurality of granular operations are used to infer the plurality of read thresholds.

15. The method of claim 12 , wherein a single atomic operation is used to infer the plurality of read thresholds.

16. The method of claim 12 , further comprising:

applying interpolation and/or extrapolation between grid of possible memory conditions and/or between recorded read thresholds.

17. The method of claim 12 , further comprising:

gathering a plurality of tuples of possible memory conditions; and

unifying the plurality of tuples.

18. The method of claim 12 , wherein the unifying comprises clustering possible memory conditions to a limited number of groups, wherein each group is related to a read threshold.

19. The method of claim 12 , wherein the memory conditions comprise one or more of the following: time and temperature group information, temperature information, bit error rate information, program-erase count (PEC) information, physical page location information, a read threshold on a representative wordline, a data retention level of a block, and a state-by-state cell-voltage-distribution measurement.

20. A storage system comprising:

a memory; and

means for:

before receiving a command to read a wordline in the memory, inferring a plurality of read thresholds from a respective plurality of sets of parameter values and conditions of the memory that may exist when the command to read the wordline in the memory is received; and

in response to receiving the command to read the wordline in the memory:

determining a present set of parameter values and conditions of the memory; and

selecting a read threshold from the plurality of read thresholds based on the present set of parameter values and conditions of the memory.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2023
From: AVRAHAM, DAVID; BAZARSKY, ALEXANDER; SHARON, ERAN; NAVON, ARIEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064792/0874 →
Continuity (5)
Continuation In Part 17838481 · Jun 13, 2022
Continuation In Part 17899073 · Aug 30, 2022
Continuation In Part 18220363 · Jul 11, 2023
Provisional Application 63421647 · Nov 2, 2022
Related Publication 20230420059A1 · Dec 28, 2023
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Cited By (2)
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