IP Library Granted Patent US 12,283,328
Granted Patent B2
US 12,283,328 · App. 17/838,481 · Granted Apr 22, 2025

Storage system and method for inference of read thresholds based on memory parameters and conditions

Inventors: Eran Sharon (Rishon Lezion, IL); Ariel Navon (Revava, IL); Alexander Bazarsky (Holon, IL); David Avraham (San Jose, CA); Nika Yanuka (Hadera, IL); Idan Alrod (Herzeliya, IL); Tsiko Shohat Rozenfeld (Los Altos, CA); Ran Zamir (Ramat Gan, IL)
Assignee: Sandisk Technologies, Inc.
G11C16/3459G11C11/1673G11C16/08G11C16/102G11C16/14G11C16/26G11C16/3495G11C29/52G11C16/0483
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Quick Facts
Patent No.
US 12,283,328
App. No.
17/838,481
Granted
Apr 22, 2025
Kind
B2
Abstract

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.

Claims (35)

1. A storage system comprising:

a memory; and

a processor coupled with the memory and configured to:

train a machine-learning model of an inference engine using state-by-state cell-voltage-distribution measurements obtained at different conditions of the memory, wherein the trained machine-learning model non-linearly couples a plurality of parameters of the memory with a respective plurality of read thresholds;

use the inference engine to infer a read threshold based on current parameters of the memory; and

use the inferred read threshold in reading a wordline in the memory.

2. The storage system of claim 1 , wherein the inference engine is used in response to a read command received from a host.

3. The storage system of claim 1 , wherein the inference engine is used in response to invoking a read error handling process.

4. The storage system of claim 1 , wherein the current parameters of the memory comprise one or more of the following: time and temperature group information, temperature information, bit error rate information, program-erase count (PEC) information, physical page location information, a read threshold on a representative wordline, a data retention level of a block, and a state-by-state cell-voltage-distribution measurement.

5. The storage system of claim 1 , wherein the inference engine in configured to infer correction to the read threshold with respect to a time and temperature group read threshold.

6. The storage system of claim 1 , wherein the machine learning model is trained in an off-line process.

7. The storage system of claim 1 , wherein the processor is further configured to:

monitor a quality of the read threshold; and

re-train the machine learning model based on the monitored quality.

8. The storage system of claim 1 , wherein the inference engine is implemented as a pure hardware implementation in a controller.

9. The storage system of claim 1 , wherein the inference engine is implemented as firmware in a controller.

10. The storage system of claim 1 , wherein the processor is further configured to use the inference engine to infer a program/verify threshold.

11. The storage system of claim 1 , wherein the processor is further configured to use the inference engine to infer a soft-bit read threshold.

12. The storage system of claim 1 , wherein the processor is further configured to use the inference engine to infer a soft-bit delta value.

13. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

14. In a storage system comprising a memory, a method comprising:

training a machine-learning model of an inference engine using state-by-state cell-voltage-distribution measurements obtained at different conditions of the memory, wherein the trained machine-learning model non-linearly couples a plurality of parameters of the memory with a respective plurality of read thresholds;

using the inference engine to infer a read threshold based on current parameters of the memory; and

using the inferred read threshold in reading a wordline in the memory.

15. The method of claim 14 , wherein the inference engine is used in response to a read command received from a host.

16. The method of claim 14 , wherein the inference engine is used as part of a read error handling (REH) process.

17. The method of claim 14 , wherein the current parameters of the memory comprise one or more of the following: time and temperature group information, temperature information, bit error rate information, program-erase count (PEC) information, physical page location information, a read threshold on a representative wordline, a data retention level of a block, and a state-by-state cell-voltage-distribution measurement.

18. The method of claim 14 , further comprising generating an inference of a program/verify threshold.

19. A storage system comprising:

a memory; and

means for:

training a machine-learning model of an inference engine using state-by-state cell-voltage-distribution measurements obtained at different conditions of the memory, wherein the trained machine-learning model non-linearly couples a plurality of parameters of the memory with a respective plurality of read thresholds;

using the inference engine to infer a read threshold based on current parameters of the memory; and

using the inferred read threshold in reading a wordline in the memory.

20. The method of claim 14 , further comprising generating an inference of one or both of a soft-bit read threshold and a soft-bit delta value.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2022
From: SHARON, ERAN; NAVON, ARIEL; BAZARSKY, ALEXANDER; AVRAHAM, DAVID; YANUKA, NIKA; ALROD, IDAN; ROZENFELD, TSIKO SHOHAT; ZAMIR, RAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060187/0490 →