IP Library Granted Patent US 10,095,412
Granted Patent B2
US 10,095,412 · App. 14/939,658 · Granted Oct 9, 2018

Memory system and method for improving write performance in a multi-die environment

Inventors: Hua-Ling Cynthia Hsu (Fremont, CA); Abhijeet Manohar (Bangalore, IN); Victor Avila (Sunnyvale, CA); Tien-Chien Kuo (Sunnyvale, CA); Jong Hak Yuh (Pleasanton, CA)
Assignee: SanDisk Technologies LLC
G06F3/061G06F1/3225G06F1/3275G06F3/0653G06F3/0659G06F3/0685G06F3/0688G06F12/0866Y02D10/13Y02D10/14
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Quick Facts
Patent No.
US 10,095,412
App. No.
14/939,658
Granted
Oct 9, 2018
Kind
B2
Abstract

A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are provided.

Claims (31)

1. A memory system comprising:

a plurality of memory dies; and

a controller in communication with the plurality of memory dies, wherein the controller is configured to:

perform the following before and after a program operation of each memory die:

send a broadcast status command to the plurality of memory dies;

receive an indication of programming status from each of the plurality of memory dies in response to the broadcast status command; and

dynamically adjust a maximum peak current limit of the plurality of memory dies based on the indication of programming status received from each of the plurality of memory dies such that memory dies whose programming status is active receive a higher maximum peak limit than those memory dies whose programming status is inactive.

2. The memory system of claim 1 , wherein a new maximum peak current limit for a memory die is contained in an address field in a message sent to the memory die.

3. The memory system of claim 1 , wherein the controller is further configured to dynamically adjust the maximum peak current limit before issuing a next program sequence.

4. The memory system of claim 1 , wherein the controller is further configured to dynamically adjust the maximum peak current limit during an ongoing program sequence.

5. The memory system of claim 1 , wherein the controller is further configured to reset the maximum peak current limit.

6. The memory system of claim 1 , wherein at least one of the plurality of memory dies comprises a three-dimensional memory.

7. The memory system of claim 1 , wherein the memory system is embedded in a host.

8. The memory system of claim 1 , wherein the memory system is removably connected to a host.

9. A method for improving write performance in a multi-die memory system, the method comprising:

performing the following before and after a program operation of each memory die in a memory system comprising a plurality of memory dies, wherein the plurality of memory dies is associated with a current budget:

sending a broadcast status command to the plurality of memory dies;

receiving an indication from each memory die as to whether each memory die is active in response to the broadcast status command; and

allocating current from the current budget only to the memory die(s) that are active, wherein the memory die(s) that are active are allocated more than their pro rata share of the current budget, thereby increasing performance of those memory die(s).

10. The method of claim 9 , wherein at least one of the plurality of memory dies comprises a three-dimensional memory.

11. The method of claim 9 , wherein the memory system is embedded in a host.

12. The method of claim 9 , wherein the memory system is removably connected to a host.

13. A memory system comprising:

a plurality of memory dies;

means for sending a broadcast status command to the plurality of memory dies before and after a program operation of each memory die;

means for receiving indications from the plurality of memory dies in response to the broadcast status command to determine how many of the plurality of memory dies are being programmed; and

means for making on-the-fly adjustments to change programming speeds of the memory dies that are being programmed based on how many of the plurality of memory dies are being programmed.

14. The memory system of claim 13 , wherein the controller is configured to make the on-the-fly adjustments by dynamically increasing or decreasing a maximum peak current limit of the plurality of memory dies based on how many of the plurality of memory dies are being programmed.

15. The memory system of claim 13 , wherein at least one of the plurality of memory dies comprises a three-dimensional memory.

16. The memory system of claim 13 , wherein the memory system is embedded in a host.

17. The memory system of claim 13 , wherein the memory system is removably connected to a host.

Assignments (5)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038812/0954 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2015
From: HSU, HUA-LING CYNTHIA; MANOHAR, ABHIJEET; AVILA, VICTOR; KUO, TIEN-CHIEN; YUH, JONG HAK
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 037030/0658 →
Continuity (1)
Related Publication 20170139590A1 · May 18, 2017
Cited By (1)
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