IP Library Granted Patent US 12,424,251
Granted Patent B2
US 12,424,251 · App. 18/220,363 · Granted Sep 23, 2025

Storage system and method for circuit-bounded-array-based time and temperature tag management and inference of read thresholds

Inventors: Alexander Bazarsky (Holon, IL); Ariel Navon (Revava, IL); Eran Sharon (Rishon Lezion, IL); David Avraham (San Jose, CA); Nika Yanuka (Hadera, IL); Idan Alrod (Herzeliya, IL)
Assignee: Sandisk Technologies, Inc.
G11C7/1069G11C7/1063G11C11/54
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Quick Facts
Patent No.
US 12,424,251
App. No.
18/220,363
Granted
Sep 23, 2025
Kind
B2
Abstract

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a circuit-bounded array is used to manage updates to time and temperature tag information and to infer read thresholds.

Claims (37)

1. A storage system comprising:

a memory comprising a plurality of memory dies, wherein each memory die comprises a respective circuit-bounded array; and

a processor coupled with the memory and configured to perform the following for each of the plurality of memory dies:

read a wordline in a memory die;

determine a read threshold based on the read wordline; and

send the read threshold to the circuit-bounded array in the memory die;

wherein each circuit-bounded array is configured to apply a machine-learning-based adjustment to the read threshold.

2. The storage system of claim 1 , wherein the wordline read by the processor is part of a time and temperature group and the circuit-bounded array is further configured to apply the machine-learning-based adjustment to the read threshold in response to the time and temperature group being read.

3. The storage system of claim 2 , wherein the processor is further configured to manage time and temperature groups of all of the plurality of memory dies.

4. The storage system of claim 3 , wherein the processor is further configured to determine the read thresholds in response to a time and temperature group update.

5. The storage system of claim 1 , wherein each circuit-bounded array is further configured to apply the machine-learning-based adjustment to the read threshold on-the-fly before reading a target wordline.

6. The storage system of claim 1 , wherein at least one circuit-bounded array uses a different machine-learning algorithm than another one of the circuit-bounded arrays.

7. The storage system of claim 1 , wherein at least one circuit-bounded array uses a machine-learning algorithm that is trained at least in part off-line.

8. The storage system of claim 1 , wherein each circuit-bounded array comprises a respective memory chip and a separate respective complementary metal oxide semiconductor (CMOS) chip.

9. The storage system of claim 1 , wherein at least one of the circuit-bounded arrays is a Circuit Above the Array (CAA) device.

10. The storage system of claim 1 , wherein at least one of the circuit-bounded arrays is a Circuit Under the Array (CUA) device.

11. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

12. In a storage system comprising a memory comprising a plurality of circuit-bounded array (CBAs), wherein each CBA includes a memory die, a method comprising:

performing the following in each CBA:

reading a wordline in a time and temperature group in the memory die of the CBA;

determining a read threshold based on the read wordline;

storing the read threshold in the CBA; and

applying a machine-learning-based adjustment to the read threshold.

13. The method of claim 12 , wherein each CBA applies the machine-learning- based adjustment to the read threshold on-the-fly before reading a target wordline.

14. The method of claim 12 , wherein each CBA comprises the respective memory die and a separate respective complementary metal oxide semiconductor (CMOS) chip coupled to the memory die.

15. The method of claim 12 , wherein each CBA determines the read threshold based on the read wordline in parallel with at least one other CBA.

16. The method of claim 12 , wherein at least one of the CBAs reads the wordline in the time and temperature group during idle time of its memory die.

17. The method of claim 12 , wherein at least one of the CBAs reads the wordline in the time and temperature group in response to receiving a command from a storage controller of the storage system.

18. The method of claim 12 , wherein at least one CBA uses a different machine-learning algorithm than another one of the CBAs.

19. The method of claim 12 , wherein at least one CBA uses a machine-learning algorithm that is trained at least in part off-line.

20. A storage system comprising:

a memory comprising a circuit-bounded array (CBA) including a memory die; and

means, located in the circuit-bounded array, for:

reading a wordline in a time and temperature group in the memory die of the CBA;

determining a read threshold based on the read wordline;

storing the read threshold in the CBA; and

applying a machine-learning-based adjustment to the read threshold.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2023
From: BAZARSKY, ALEXANDER; NAVON, ARIEL; SHARON, ERAN; AVRAHAM, DAVID; YANUKA, NIKA; ALROD, IDAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064215/0031 →
Continuity (4)
Continuation In Part 17838481 · Jun 13, 2022
Continuation In Part 17899073 · Aug 30, 2022
Provisional Application 63421647 · Nov 2, 2022
Related Publication 20230402072A1 · Dec 14, 2023
References Cited (50)
US 6154157A · Wong · 2000 [cited by examiner]
US 7876671B2 · Pimlott · 2011 [cited by applicant]
US 7995387B2 · Sharon et al. · 2011 [cited by applicant]
US 8374026B2 · Sharon et al. · 2013 [cited by applicant]
US 8782495B2 · Alrod et al. · 2014 [cited by applicant]
US 9070479B2 · Sharon et al. · 2015 [cited by applicant]
US 9141475B2 · Alrod et al. · 2015 [cited by applicant]
US 9431120B1 · Tuers · 2016 [cited by examiner]
US 9697905B2 · Sharon et al. · 2017 [cited by applicant]
US 9728263B2 · Sharon · 2017 [cited by applicant]
US 9996281B2 · Sharon et al. · 2018 [cited by applicant]
US 10379739B1 · Bazarsky et al. · 2019 [cited by applicant]
US 10418097B2 · Avraham et al. · 2019 [cited by applicant]
US 10475523B2 · Sharon et al. · 2019 [cited by applicant]
US 10811091B2 · Bazarsky et al. · 2020 [cited by applicant]
US 10991444B1 · Bazarsky et al. · 2021 [cited by applicant]
US 11081474B1 · Hoang et al. · 2021 [cited by applicant]
US 11150825B2 · Kashyap et al. · 2021 [cited by applicant]
US 11244732B2 · Sharon et al. · 2022 [cited by applicant]
US 20120063227A1 · Weingarten et al. · 2012 [cited by applicant]
US 20140056066A1 · Baum et al. · 2014 [cited by applicant]
US 20140136927A1 · Li · 2014 [cited by applicant]
US 20170139590A1 · Hsu et al. · 2017 [cited by applicant]
US 20170162268A1 · Chen et al. · 2017 [cited by applicant]
US 20180293029A1 · Achtenberg · 2018 [cited by applicant]
US 20180293174A1 · Song · 2018 [cited by applicant]
US 20190189236A1 · Poliakov et al. · 2019 [cited by applicant]
US 20190371402A1 · Lin · 2019 [cited by applicant]
US 20200364108A1 · Froelich et al. · 2020 [cited by applicant]
US 20200364118A1 · Sun · 2020 [cited by applicant]
US 20210241845A1 · Li · 2021 [cited by examiner]
US 20210334035A1 · Sheperek et al. · 2021 [cited by applicant]
US 20220027721A1 · Zhang et al. · 2022 [cited by applicant]
US 20220075561A1 · Peltz et al. · 2022 [cited by applicant]
US 20220076738A1 · Bazarsky · 2022 [cited by applicant]
US 20220121387A1 · Ha et al. · 2022 [cited by applicant]
US 20220121985A1 · Lloyd et al. · 2022 [cited by applicant]
US 20220254419A1 · Kim et al. · 2022 [cited by applicant]
US 20250118376A1 · Shenoy · 2025 [cited by applicant]
U.S. Appl. No. 17/838,481, filed Jun. 13, 2022, entitled “Storage System and Method for Inference of Read Thresholds Based on Memory Parameters and Conditions.” [cited by applicant]
U.S. Appl. No. 17/899,073, filed Aug. 30, 2022, entitled “Storage System and Method for Implementation of Symmetric Tree Models for Read Threshold Calibration.” [cited by applicant]
U.S. Appl. No. 18/239,302, filed Aug. 29, 2023, entitled “Data Storage Device and Method for Inferring a Read Threshold Using a Time Tag Determination.” [cited by applicant]
U.S. Appl. No. 18/242,061, filed Sep. 5, 2023, entitled “Data Storage Device and Method for Predicting Future Read Thresholds.” [cited by applicant]
U.S. Appl. No. 18/777,942, filed Jul. 19, 2024, entitled “Data Storage Device and Method for Using Multiple Models for Predicting a Read Threshold.” [cited by applicant]
U.S. Appl. No. 18/800,681, filed Aug. 12, 2024, entitled “Data Storage Device and Method for Combining Prediction Models for Read Threshold Calibration.” [cited by applicant]
U.S. Appl. No. 18/664,514, filed May 15, 2024, entitled “Data Storage Device and Method for Generating Read Threshold Voltages.” [cited by applicant]
U.S. Appl. No. 18/658,074, filed May 8, 2024, entitled “Data Storage Device and Method for Predictive Read Threshold Calibration.” [cited by applicant]
U.S. Appl. No. 18/772,563, filed Jul. 15, 2024, entitled “Data Storage Device and Method for Using Modular Models for Inferring a Read Threshold.” [cited by applicant]
Non-final Office Action mailed Jun. 16, 2025 for U.S. Appl. No. 18/664,514. [cited by applicant]
Non-final Office Action mailed Jun. 16, 2025 for U.S. Appl. No. 18/242,061. [cited by applicant]