Multi-level loop cut process for a three-dimensional memory device using pitch-doubled metal lines
First elongated loop-shaped conductive material portions are formed over a substrate. A two-dimensional array of memory pillar structures is formed over the first elongated loop-shaped conductive material portions. Second elongated loop-shaped conductive material portions over the two-dimensional array of memory pillar structures. Each of the elongated loop-shaped conductive material potions includes a respective pair of line segments and a respective pair of end segments adjoined to ends of the respective pair of line segments. A moat trench that at least partially laterally encloses the two-dimensional array of memory pillar structures can be formed by performing an anisotropic etch process that removes parts of the first and second elongated loop-shaped conductive material portions, thereby separating each loop-shaped conductive material portion into two disjoined line segments.
1. A method of forming a device structure, comprising:
forming first elongated loop-shaped conductive material portions over a substrate, wherein each of the first elongated loop-shaped conductive material potions includes a respective pair of first line segments and a respective pair of first end segments adjoined to ends of the respective pair of first line segments;
forming a two-dimensional array of memory pillar structures over the first elongated loop-shaped conductive material portions;
forming second elongated loop-shaped conductive material portions over the two-dimensional array of memory pillar structures, wherein each of the second elongated loop-shaped conductive material potions includes a respective pair of second line segments and a respective pair of second end segments adjoined to ends of the respective pair of second line segments;
forming an electrically conductive material layer on top surfaces of the second elongated loop-shaped conductive material portions; and
forming a moat trench that at least partially laterally encloses the two-dimensional array of memory pillar structures by performing an anisotropic etch process that removes, in sequential order, a peripheral portion of the electrically conductive material layer, parts of the second elongated loop-shaped conductive material portions, and parts of the first elongated loop-shaped conductive material portions.
2. The method of claim 1 , further comprising:
forming a patterned etch mask layer over the electrically conductive material layer within an area that covers the two-dimensional array of memory pillar structures, wherein the peripheral region of the electrically conductive material layer, the parts of the second elongated loop-shaped conductive material portions, and the parts of the first elongated loop-shaped conductive material portions that are removed by the anisotropic etch process are located within areas that are not masked by the patterned etch mask layer.
3. The method of claim 2 , wherein:
the patterned etch mask layer comprises a lithographically patterned photoresist layer having a rectangular horizontal cross-sectional shape; and
the anisotropic etch process removes each of the second end segments, and each of the first end segments.
4. The method of claim 1 , wherein:
each of the first line segments laterally extends along a first horizontal direction; and
each of the second line segments laterally extend along a second horizontal direction.
5. The method of claim 4 , wherein:
remaining portions of the first elongated loop-shaped conductive material portions after the anisotropic etch process comprises first conductive line structures that extend along the first horizontal direction and having a uniform first pitch along the second horizontal direction; and
remaining portions of the second elongated loop-shaped conductive material portions after the anisotropic etch process comprises second conductive line structures that extend along the second horizontal direction and having a uniform second pitch along first horizontal direction.
6. The method of claim 5 , wherein:
the first elongated loop-shaped conductive material portions are formed as a periodic one-dimensional array having a periodicity that is twice the uniform first pitch along the second horizontal direction; and
the second elongated loop-shaped conductive material portions are formed as a periodic one-dimensional array having a periodicity that is twice the uniform second pitch along the first horizontal direction.
7. The method of claim 4 , further comprising:
forming a first blanket electrically conductive layer over the substrate;
forming first template line structures extending along the first horizontal direction over the first blanket electrically conductive layer;
forming first etch mask spacer structures around each of the first template line structures;
removing the first template line structures selective to the first etch mask spacer structures and the first blanket electrically conductive layer; and
transferring patterns in the first etch mask spacer structures through the first blanket electrically conductive layer, wherein remaining patterned portions of the first blanket electrically conductive layer constitute the first elongated loop-shaped conductive material portions.
8. The method of claim 7 , wherein the template line structures are formed by:
applying and lithographically patterning a template material layer over the first blanket electrically conductive layer; and
isotropically recessing remaining lithographically patterned portions of the template material layer to provide the template line structures.
9. The method of claim 7 , further comprising:
forming lower first-level dielectric isolation structures between the first elongated loop-shaped conductive material portions;
forming a second lower blanket electrically conductive layer over the lower first-level dielectric isolation structures between the first elongated loop-shaped conductive material portions;
forming second template line structures extending along the second horizontal direction over the second lower blanket electrically conductive layer;
forming second etch mask spacer structures around each of the second template line structures;
removing the second template line structures selective to the second etch mask spacer structures and the second lower blanket electrically conductive layer; and
transferring patterns in the second etch mask spacer structures through the second lower blanket electrically conductive layer, wherein remaining patterned portions of the second lower blanket electrically conductive layer constitute the second elongated loop-shaped conductive material portions.
10. The method of claim 2 , further comprising patterning a remaining portion of the electrically conductive material layer that remains after the anisotropic etch process into third line segments that contact a top surface of a respective one of the second line segments by performing an additional anisotropic etch process, wherein the third line segments are arranged as a one-dimensional periodic array having the uniform second pitch along the first horizontal direction.
11. The method of claim 10 , further comprising:
forming template line structures extending along the second horizontal direction over the remaining portion of the electrically conductive material layer and over the two-dimensional array of memory pillar structures after the anisotropic etch process;
forming etch mask spacer structures around each of the template line structures;
removing the template line structures selective to the etch mask spacer structures and the electrically conductive material layer; and
transferring patterns in the etch mask spacer structures through the remaining portion of the electrically conductive material layer employing a pattern transfer process, wherein remaining patterned portions of the electrically conductive layer constitute third line segments.
12. The method of claim 11 , wherein:
each of the third line segments contacts a top surface of a respective one of the second line segments; and
the third line segments have a same periodicity along the first horizontal direction as the second line segments.
13. The method of claim 3 , further comprising forming a dielectric moat structure by depositing a dielectric material in the moat trench and by removing an excess portion of the dielectric material from above a horizontal plane including a top surface of a remaining portion of the electrically conductive material layer after the anisotropic etch process.
14. The method of claim 13 , wherein:
the moat trench completely laterally encloses the two-dimensional array of memory pillar structures; and
each of the first line segments and each of the second line segments contacts a respective pair of sidewalls of the dielectric moat structure.
15. The method of claim 1 , wherein each memory pillar structure within the two-dimensional array of memory pillar structures comprises:
a memory element comprising a memory material configured to provide at least two different states representing a respective bit; and
a selector element.
16. The method of claim 15 , wherein:
the memory material comprises a phase change memory material; and
the selector element comprises an ovonic threshold voltage material.
17. The method of claim 16 , further comprising forming a first dielectric matrix around the two-dimensional array of memory pillar structures, wherein the second elongated loop-shaped conductive material portions are formed within an upper region of the first dielectric matrix.
18. The method of claim 1 , further comprising:
forming underlying elongated loop-shaped conductive material portions over the substrate, wherein each of the underlying elongated loop-shaped conductive material potions includes a respective pair of underlying line segments and a respective pair of underlying end segments adjoined to ends of the respective pair of underlying line segments, and wherein each of the first loop-shaped conductive material portions is formed over a respective one of the underlying elongated loop-shaped conductive material portions; and
removing the underlying end segments employing the anisotropic etch process.
19. The method of claim 1 , wherein:
each memory pillar structure within the two-dimensional array of memory pillar structures is configured to be individually accessed by a combination of a respective word line and a respective bit line; and
the device structure has a configuration selected from:
a first configuration in which the bit lines comprise the first line segments and the word lines comprise the second line segments; or
a second configuration in which the word lines comprise the first line segments and the bit lines comprise the second line segments.
20. The method of claim 1 further comprising forming dielectric isolation structures between and on sidewalls of the second elongated loop-shaped conductive material portions, wherein:
the dielectric isolation structures have top surfaces within a horizontal plane including top surfaces of the second elongated loop-shaped conductive material portions;
the electrically conductive material layer is formed on top surfaces of the dielectric isolation structures and a bottom surface of the electrically conductive material layer contacts an entirety of each top surface of second elongated loop-shaped conductive material portions;
after performing the anisotropic etch process, a remaining portion of the electrically conductive material layer comprises a single conductive plate that contacts top surfaces of remaining portions of the second elongated loop-shaped conductive material portions; and
the single conductive plate contacts top surfaces of remaining portions of the dielectric isolation structures after performing the anisotropic etch process.