IP Library Granted Patent US 10,698,839
Granted Patent B2
US 10,698,839 · App. 15/962,766 · Granted Jun 30, 2020

Seed scrambling

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Quick Facts
Patent No.
US 10,698,839
App. No.
15/962,766
Granted
Jun 30, 2020
Kind
B2
Abstract

Apparatuses, systems, methods, and computer program products are disclosed for seed scrambling. An apparatus includes a memory element. An apparatus includes a scrambler component. A scrambler component includes an input circuit that receives a random seed. A scrambler component includes a matrix circuit that generates a new seed based on a matrix operation performed on a seed. A scrambler component includes a rotation circuit that forms a shifted seed. A shifted seed is formed by shifting a new seed based on a seed.

Claims (26)

1. An apparatus comprising:

a memory element; and

a scrambler component comprising:

an input circuit that receives a seed;

a matrix circuit that generates a new seed based on a matrix operation performed on the seed; and

a rotation circuit that forms a shifted seed, wherein the shifted seed is formed by shifting the new seed a number of bit positions determined based on the seed, the rotation circuit comprises a first rotation circuit and a second rotation circuit, and the first rotation circuit rotates the new seed in a first direction in a first vector and the second rotation circuit shifts the new seed in a second direction in a second vector, wherein the first direction is different from the second direction.

2. The apparatus of claim 1 , wherein the scrambler component comprises a second matrix circuit that performs a second matrix operation and generates a scrambling vector based on the second matrix operation, and the second matrix operation is performed on either the shifted seed or the new seed.

3. The apparatus of claim 2 , wherein the first rotation circuit and the second rotation circuit generate a shifted scrambling vector based on a third matrix operation performed on the scrambling vector.

4. The apparatus of claim 1 , wherein the seed comprises an initial seed.

5. The apparatus of claim 1 , wherein the seed comprises a previously used seed.

6. The apparatus of claim 1 , wherein the matrix operation comprises matrix multiplication.

7. The apparatus of claim 1 , wherein the first vector is different from the second vector.

8. The apparatus of claim 1 , further comprising a scaling circuit that receives an output from the first rotation circuit and provides an input to the second rotation circuit.

9. The apparatus of claim 1 , wherein the first rotation circuit shifts the new seed in the first vector based on a first portion of the seed and the second rotation circuit shifts the new seed in the second vector based on a second portion of the seed.

10. A method comprising:

receiving a previous seed used for scrambling data;

generating a new seed for scrambling data using matrix multiplication of the previous seed; and

modifying the new seed by applying one or more rotation functions to the new seed a number of bit positions determined based on the previous seed to result in an adjusted new seed, wherein the one or more rotation functions comprise a first rotation function and a second rotation function, the first rotation function rotates the new seed in a first direction to result in a rotated new seed, and the second rotation function rotates a seed resulting from an operation on the rotated new seed in a second direction to result in the adjusted new seed, wherein the first direction is different from the second direction.

11. The method of claim 10 , wherein the function comprises a multiplication function.

12. The method of claim 11 , wherein the multiplication function multiplies an input seed by a matrix.

13. An apparatus comprising:

means for receiving an initial seed and a previous seed;

means for selecting one of the initial seed or the previous seed as a reference seed;

means for generating an intermediate seed using matrix multiplication of the reference seed; and

means for performing one or more functions on the intermediate seed to produce a current seed, the one or more functions comprising altering an order of bits of the intermediate seed to produce the current seed, the altered order of the bits comprising a number of bit positions determined based on the reference seed, wherein the means for performing the one or more functions comprise a first rotation function and a second rotation function, the first rotation function rotates the intermediate seed in a first direction to result in a rotated intermediate seed, and the second rotation function rotates a seed resulting from an operation on the rotated intermediate seed in a second direction to result in the current seed, wherein the first direction is different from the second direction.

14. The method of claim 13 , wherein the means for performing the one or more functions comprises means for shifting an order of bits of the intermediate seed a plurality of times based on the reference seed to produce the current seed.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2018
From: ILANI, ISHAI; SHARON, ERAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 047639/0889 →