Memory modules with multi-chip packaged integrated circuits having flash memory
View Patent ↗A memory module is provided. In one example, the memory module includes a printed circuit board with one or more connectors, and a plurality of multi-chip packaged integrated circuit parts mounted to the printed circuit board. Each of the plurality of multi-chip packaged integrated circuit parts includes an integrated circuit package including a slave memory controller (SMC) die and one or more pairs of (1) a spacer under the slave memory controller die and (2) a flash memory die under the spacer. Each flash memory die is larger than each spacer to provide an opening into a perimeter of the flash memory die to which electrical connections may be made.
1. A memory module comprising:
a printed circuit board (PCB) with one or more connectors;
a plurality of multi-chip packaged integrated circuit parts mounted to the printed circuit board, each of the plurality of multi-chip packaged integrated circuit parts comprising:
an integrated circuit package including
a slave memory controller (SMC) die, and
one or more pairs of
a spacer under the slave memory controller die, and
a flash memory die under the spacer,
wherein each flash memory die is larger than each spacer to provide an opening into a perimeter of the flash memory die to which electrical connections may be made.
2. The memory module of claim 1 , wherein
the integrated circuit package is a multi-chip module integrated circuit package.
3. The memory module of claim 1 , wherein
one connector of the one or more connectors of the printed circuit board are on one side of the printed circuit board, and
another connector of the one or more connectors of the printed circuit board are on an opposite side of the printed circuit board.
4. The memory module of claim 1 , wherein
one connector of the one or more connectors of the printed circuit board are on one side of the printed circuit board, and
another connector of the one or more connectors of the printed circuit board are on the one side of the printed circuit board.
5. The memory module of claim 1 , wherein the integrated circuit package of each of the plurality of multi-chip packaged integrated circuit parts further includes
a first plurality of conductors to electrically coupled the slave memory controller die to one or more independent pads of a pin-out of the integrated circuit package;
a second plurality of conductors to electrically couple the slave memory controller die to one or more joint pads of the pin-out; and
a third plurality of conductors to electrically couple one or more of the flash memory die to the one or more joint pads of the pin-out to electrically couple the flash memory die to the slave memory control die.
6. The memory module of claim 1 , wherein the spacers in the integrated circuit package of each of the plurality of multi-chip packaged integrated circuit parts is a dielectric or insulator so active portions of the circuitry of the flash memory die do not short to active portions of a neighboring integrated circuit die.
7. The memory module of claim 1 , wherein the slave memory controller die in the integrated circuit package of each of the plurality of multi-chip packaged integrated circuit parts includes a processor.
8. The memory module of claim 7 , wherein
the slave memory controller die in the integrated circuit package of each of the plurality of multi-chip packaged integrated circuit parts further includes a scratch pad memory coupled to the processor.
9. The memory module of claim 1 , wherein the integrated circuit package of each of the plurality of multi-chip packaged integrated circuit parts further includes
a processor, and
a scratch pad memory coupled to the processor.
10. The memory module of claim 1 , wherein the integrated circuit package of each of the plurality of multi-chip packaged integrated circuit parts further includes under the slave memory controller die and over the one or more pairs of the spacer and the flash memory die,
a first spacer;
a processor under the first spacer;
a second spacer under the processor; and
a scratch pad memory die under the second spacer.