IP Library Granted Patent US 9,836,215
Granted Patent B2
US 9,836,215 · App. 14/548,115 · Granted Dec 5, 2017

Real time protocol generation

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Quick Facts
Patent No.
US 9,836,215
App. No.
14/548,115
Granted
Dec 5, 2017
Kind
B2
Abstract

A storage device may include a memory; and a controller. The controller may be configured to: maintain, for each respective type of command segment of a plurality of types of command segments, a respective timer of a plurality of timers that indicates an amount of time elapsed since the controller last output a command segment of the respective type of command segments to the memory; determine, based on the plurality of timers, whether a command segment of a particular type of command segment of the plurality of types of command segments may be output to the memory at a current time; and responsive to determining that the command segment of the particular type of command segment may be output at the current time, permit output of the command segment of the particular type of command segment to the memory at the current time.

Claims (70)

1. A data storage device, comprising:

a non-volatile memory array arranged into a plurality of channels; and

a controller configured to:

maintain, for each respective type of command segment of a plurality of types of command segments, a respective timer of a first plurality of timers that indicates an amount of time elapsed since the controller last output a command segment of the respective type of command segments to a first channel of the non-volatile memory array;

maintain a table of delay values pertaining to an amount of time between which the controller may output commands to a validation module;

determine through the validation module, based on the first plurality of timers and the table of delay values, whether a command segment of a particular type of command segment of the plurality of types of command segments may be output to the first channel of the non-volatile memory array at a current time; and

responsive to determining that the command segment of the particular type of command segment may be output to the first channel of the non-volatile memory array at the current time, permit output of the command segment of the particular type of command segment to the first channel of the non-volatile memory array at the current time.

2. The data storage device of claim 1 , wherein the controller is further configured to determine whether the command segment of the particular type of command segment may be output to the first channel of the non-volatile memory array at the current time by at least:

determining a plurality of delay values that each indicate a respective minimum amount of time between a time at which the controller outputs a command segment of a respective type of command segment of the plurality of types of command segments and a time at which the controller may output the particular type of command segment to the first channel of the non-volatile memory array;

determining that the command segment of the particular type of command segment may be output to the first channel of the non-volatile memory array at the current time responsive to determining that a value of each respective timer of the first plurality of timers satisfies a corresponding delay value of the plurality of delay values; and

determining that the command segment of the particular type of command segment may not be output to the first channel of the non-volatile memory array at the current time responsive to determining that a value of at least one timer of the first plurality of timers does not satisfy the corresponding delay value of the plurality of delay values.

3. The data storage device of claim 2 , wherein, the controller is configured to, responsive to determining that the command segment of the particular type of command segments may not be output to the first channel of the non-volatile memory array at the current time, delay output of the command segment of the particular type of command segment to the first channel of the non-volatile memory array until a value of each respective timer of the first plurality of timers satisfies the corresponding delay value of the plurality of delay values.

4. The data storage device of claim 2 , wherein the controller is configured to select each delay value of the plurality of delay values from a plurality of delay values that each indicate a respective minimum amount of time between times at which the controller may output various combinations of the plurality of types of command segments.

5. The data storage device of claim 1 , wherein the particular type of command segments is a second type of command segment, wherein the controller determines that the command segment of the second type of command segment may be output to the first channel of the non-volatile memory array at the current time, and wherein the controller is further configured to:

determine, based on the first plurality of timers, that a command segment of a third type of command segments of the plurality of types of command segments may not be output at the current time.

6. The data storage device of claim 1 , wherein the plurality of types of command segments include one or more of:

a chip enable (CE) segment,

a command (CMD) segment,

an address (ADR) segment,

a data write (DW) segment, or

a data read (DR) segment.

7. The data storage device of claim 1 , wherein the controller is further configured to:

determine, based on a second plurality of timers for a second channel of the non-volatile memory array, whether a command segment of a particular type of command segment of the plurality of types of command segments may be output to a second channel of the non-volatile memory array at a current time; and

responsive to determining that the command segment of the particular type of command segment may be output to the second channel of the non-volatile memory array at the current time, permit output of the command segment of the particular type of command segment to the second channel of the non-volatile memory array at the current time.

8. The data storage device of claim 1 , wherein each channel of the plurality of channels comprises a respective plurality of non-volatile memory devices that share one or more connections to the controller, and wherein the one or more connections include a common input/output bus and a common control bus.

9. The data storage device of claim 1 , wherein the controller is configured to maintain a separate plurality of timers for each respective channel of the plurality of channels.

10. A method comprising:

maintaining, for each respective type of command segment of a plurality of types of command segments, a respective timer of a first plurality of timers that indicates an amount of time elapsed since a controller of a data storage device last output a command segment of the respective type of command segment to a first channel of a plurality of channels of a non-volatile memory array of the data storage device;

maintaining a table of delay values pertaining to an amount of time between which the controller may output commands to a validation module;

determining through the validation module, based on the first plurality of timers and the table of delay values, whether a command segment of a particular type of command segment of the plurality of types of command segments may be output to the first channel of the non-volatile memory array at a current time; and

responsive to determining that the command segment of the particular type of command segment may be output at the current time, permitting output of the command segment of the particular type of command segment to the first channel of the non-volatile memory array at the current time.

11. The method of claim 10 , wherein determining whether the command segment of the particular type of command segment may be output to the first channel of the non-volatile memory array at the current time comprises:

determining a plurality of threshold values that each indicate a respective minimum amount of time between a time at which the controller outputs a command segment of a respective type of command segment of the plurality of types of command segment and a time at which the controller may output the particular type of command segment to the first channel of the non-volatile memory array;

determining that the command segment of the particular type of command segment may be output to the first channel of the non-volatile memory array at the current time in response to determining that a value of each respective timer of the first plurality of timers satisfies a corresponding threshold value of the plurality of threshold values; and

determining that the command segment of the particular type of command segment may not be output to the first channel of the non-volatile memory array at the current time in response to determining that a value of at least one timer of the first plurality of timers does not satisfy the corresponding threshold value of the plurality of threshold values.

12. The method of claim 11 , further comprising:

responsive to determining that the command segment of the particular type of command segment may not be output to the first channel of the non-volatile memory array at the current time, delaying output of the command segment of the particular type of command segment to the first channel of the non-volatile memory array until a value of each respective timer of the first plurality of timers satisfies the corresponding threshold value of the plurality of threshold values.

13. The method of claim 11 , wherein each threshold value of the plurality of threshold values is selected from a plurality of predetermined threshold values that each indicate a respective minimum amount of time between times at which the controller may issue various combinations of the plurality of types of command segments.

14. The method of claim 10 , wherein the particular type of command segments is a second type of command segments, wherein the command segment of the second type of command segments may be output to the first channel of the non-volatile memory array at the current time, and wherein the method further comprises:

determining, based on the plurality of timers, that a command segment of a third type of command segments of the plurality of types of command segments may not be output to the first channel of the non-volatile memory array at the current time.

15. The method of claim 10 , wherein the plurality of types of command segments include one or more of:

a chip enable (CE) segment,

a command (CMD) segment,

an address (ADR) segment,

a data write (DW) segment, or

a data read (DR) segment.

16. The method of claim 10 , wherein the controller is configured to maintain a separate plurality of timers for each respective channel of the plurality of channels.

17. A computer-readable storage medium storing instructions that, when executed, cause a controller of a data storage device to:

maintain, for each respective type of command segment of a plurality of types of command segments, a respective timer of a first plurality of timers that indicates an amount of time elapsed since a controller of a data storage device last output a command segment of the respective type of command segment to a first channel of a plurality of channels of a non-volatile memory array of the data storage device;

maintain a table of delay values pertaining to an amount of time between which the controller may output commands to a validation module;

determine through the validation module, based on the plurality of timers and the table of delay values, whether a command segment of a particular type of command segment of the plurality of types of command segments may be output to the first channel of the non-volatile memory array at a current time; and

responsive to determining that the command segment of the particular type of command segment may be output at the current time, permit output of the command segment of the particular type of command segment to the first channel of the non-volatile memory array at the current time.

18. The computer-readable storage medium of claim 17 , wherein the instructions that cause the controller to determine whether the command segment of the particular type of command segment may be output to the first channel of the non-volatile memory array at the current time comprise instructions that cause the controller to:

determine a plurality of threshold values that each indicate a respective minimum amount of time between a time at which the controller outputs a command segment of a respective type of command segment of the plurality of types of command segments and a time at which the controller may output the particular type of command segment to the first channel of the non-volatile memory array;

determine that the command segment of the particular type of command segment may be output to the first channel of the non-volatile memory array at the current time in response to determining that a value of each respective timer of the first plurality of timers satisfies a corresponding threshold value of the plurality of threshold values; and

determine that the command segment of the particular type of command segment may not be output to the first channel of the non-volatile memory array at the current time in response to determining that a value of at least one timer of the first plurality of timers does not satisfy the corresponding threshold value of the plurality of threshold values.

19. The computer-readable storage medium of claim 18 , further comprising instructions that cause the controller to delay, responsive to determining that the command segment of the particular type of command segment may not be output to the first channel of the non-volatile memory array at the current time, output of the command segment of the particular type of command segment to the first channel of the non-volatile memory array until a value of each respective timer of the first plurality of timers satisfies the corresponding threshold value of the plurality of threshold values.

20. The computer readable storage medium of claim 17 , wherein the instructions cause the controller to maintain a separate plurality of timers for each respective channel of the plurality of channels.

21. A system comprising:

means for maintaining, for each respective type of command segment of a plurality of types of command segments, a respective timer of a first plurality of timers that indicates an amount of time elapsed since a controller of a data storage device last output a command segment of the respective type of command segments to a first channel of a plurality of channels of a non-volatile memory array of the data storage device;

means for maintaining a table of delay values pertaining to an amount of time between which the controller may output commands to a validation module;

means for determining through the validation module, based on the first plurality of timers and the table of delay values, whether a command segment of a particular type of command segment of the plurality of types of command segments may be output to the first channel of the non-volatile memory array at a current time; and

means for responsive to determining that the command segment of the particular type of command segment may be output at the current time, permitting output of the command segment of the particular type of command segment to the first channel of the non-volatile memory array at the current time.

22. The system of claim 21 , wherein the means for determining whether the command segment of the particular type of command segments of the plurality of types of command segment may be output to the first channel of the non-volatile memory array at the current time comprise:

means for determining a plurality of threshold values that each indicate a respective minimum amount of time between a time at which the controller outputs a command segment of a respective type of command segment of the plurality of types of command segments and a time at which the controller may output the particular type of command segment to the first channel of the non-volatile memory array;

means for determining that the command segment of the particular type of command segment may be output to the first channel of the non-volatile memory array at the current time in response to determining that a value of each respective timer of the first plurality of timers satisfies a corresponding threshold value of the plurality of threshold values; and

means for determining that the command segment of the particular type of command segment may not be output to the first channel of the non-volatile memory array at the current time in response to determining that a value of at least one timer of the first plurality of timers does not satisfy the corresponding threshold value of the plurality of threshold values.

23. The system of claim 22 , further comprising:

means for delaying, responsive to determining that the command segment of the particular type of command segment may not be output to the first channel of the non-volatile memory array at the current time, output of the command segment of the particular type of command segment to the first channel of the non-volatile memory array until a value of each respective timer of the first plurality of timers satisfies the corresponding threshold value of the plurality of threshold values.

24. The system of claim 21 , wherein the means for maintaining is configured to maintain a separate plurality of timers for each respective channel of the plurality of channels.

Assignments (11)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040829/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2014
From: NOWAK, BRIAN T.
To: HGST NETHERLANDS B.V.
Reel/Frame 034213/0567 →