Corruption-preventative programming in solid-state data storage
View Patent ↗A device includes a non-volatile solid-state memory array comprising a plurality of blocks, each of the plurality of blocks configured to store data in a single-bit per cell mode or a multiple-bit per cell mode, and a controller. The controller is configured to receive write data from a host device, program the write data to a first block of the plurality of blocks of the memory array using the single-bit per cell mode, and perform a data consolidation operation on the first block at least in part by programming at least a portion of the write data together with data stored in a separate second block of the memory array to a third block of the memory array using the multiple-bit per cell mode.
1. A device comprising:
a non-volatile solid-state memory array comprising a plurality of blocks, each of the plurality of blocks configured to store data in a single-bit per cell mode or a multiple-bit per cell mode; and
a controller configured to:
receive write data from a host device;
program the write data to a first block of the plurality of blocks of the memory array using the single-bit per cell mode; and
perform a data consolidation operation on the first block at least in part by re-programming at least a portion of the write data together with data stored in a separate second block of the memory array to a third block of the memory array using the multiple-bit per cell mode.
2. The device of claim 1 , wherein the data consolidation operation is a garbage collection operation.
3. The device of claim 1 , wherein the data stored in the second block is stored in the second block using the single-bit per cell mode.
4. The device of claim 1 , wherein the controller is further configured to recover the at least a portion of the write data from the first block when a failure condition is encountered while re-programming the at least a portion of the write data to the third block.
5. The device of claim 1 , wherein a write data-to-parity data ratio of the first block is greater than a write-data-to-parity-data ratio of the third block.
6. The device of claim 1 , wherein the controller is further configured to maintain stale count data associated with the plurality of blocks of the non-volatile solid-state memory array.
7. The device of claim 6 , wherein the controller is further configured to modify a stale count associated with the first block to indicate that the first block is programmed using the single-bit per cell mode.
8. The device of claim 1 , wherein the controller is further configured to maintain information associated with the plurality of blocks of the non-volatile solid-state memory array that indicates a number of times each of the plurality of blocks has been programmed using the single-bit per cell mode.
9. The device of claim 1 , wherein the controller is further configured to prevent the first block from being programmed again using the single-bit per cell mode within a predetermined relaxation time period after completion of said data consolidation operation.
10. The device of claim 1 , wherein the controller is further configured to maintain a ready block list and to set length of the ready block list to a predetermined value.
11. A data storage device comprising:
a non-volatile solid-state memory array comprising a plurality of blocks, each of the plurality of blocks configured to store data in a single-bit per cell mode or a multiple-bit per cell mode;
means for receiving write data from a host device;
means for programming the write data to a first block of the plurality of blocks of the memory array using the single-bit per cell mode; and
means for performing a data consolidation operation on the first block at least in part by re-programming at least a portion of the write data together with data stored in a separate second block of the plurality of blocks to a third block of the plurality of blocks using the multiple-bit per cell mode.
12. The data storage device of claim 11 , wherein the means for programming the write data to the first block of the plurality of blocks comprises a controller including data storage storing instructions and one or more processors configured to execute the instructions, wherein the instructions, when executed by the one or more processors, cause the one or more processors to perform said programming the write data to the first block.
13. The data storage device of claim 11 , wherein a write data-to-parity data ratio of the first block is greater than a write-data-to-parity-data ratio of the third block.
14. A method of storing data in a data storage system, the method comprising:
receiving write data from a host device;
programming the write data to a first block of a non-volatile solid-state memory module using single-bit per cell programming; and
performing a data consolidation operation on the first block at least in part by re-programming at least a portion of the write data together with data stored in a separate second block of the non-volatile solid-state memory module to a third block of the non-volatile solid-state memory module using multiple-bit per cell programming;
wherein the method is performed using a controller of the data storage system.
15. The method of claim 14 , further comprising recovering the at least a portion of the write data from the first block when a failure condition is encountered while re-programming the at least a portion of the write data to the third block.
16. The method of claim 14 , wherein a write data-to-parity data ratio of the first block is greater than a write data-to-parity data ratio of the third block.
17. The method of claim 14 , further comprising augmenting a stale count associated with the first block to indicate that the first block is programmed using single-bit per cell programming.
18. The method of claim 14 , further comprising preventing the first block from being programmed again using single-bit per cell programming within a predetermined relaxation time period after completion of said data consolidation operation.
19. The method of claim 14 , further comprising maintaining stale count data associated with the first, second and third blocks of the non-volatile solid-state memory array.
20. The method of claim 19 , further comprising modifying a stale count associated with the first block to indicate that the first block is programmed using single-bit per cell programming.