IP Library Granted Patent US 11,393,735
Granted Patent B2
US 11,393,735 · App. 16/277,180 · Granted Jul 19, 2022

Semiconductor device including reinforced corner supports

Inventors: Yangming Liu (Shanghai, CN); Ning Ye (San Jose, CA); Chin-Tien Chiu (Taichung, TW)
Assignee: Western Digital Technologies, Inc.
H01L23/32H01L23/562H01L25/0657H01L25/50H01L2225/0651H01L2225/06506H01L2225/06562H01L2225/06586
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Quick Facts
Patent No.
US 11,393,735
App. No.
16/277,180
Granted
Jul 19, 2022
Kind
B2
Abstract

A semiconductor device is disclosed having reinforced supports at corners of the device. The semiconductor device may include solder balls on a lower surface of the device for soldering the device onto a printed circuit board. In one example, the solder balls at the corners of the semiconductor device may be replaced by support billets having more mass and more contact area between the semiconductor device and the PCB. In a further example, screws may be provided at the corners of the device (instead of the corner solder balls or in addition to the corner solder balls). These screws may be placed through the corners of the semiconductor device and into the printed circuit board.

Claims (36)

1. A semiconductor device, comprising:

a substrate comprising a dielectric core between first and second conductive layers, the substrate further having first and second opposed surfaces, the substrate comprising:

solder balls on the first surface of the substrate, the solder balls being in direct contact with one of the first and second conductive layers of the substrate and configured to couple the semiconductor device to a host device, and

corner structural supports in direct contact with the substrate at corners of the substrate, the corner structural supports having a higher strength than the solder balls; and

one or more semiconductor dies coupled to the second surface of the substrate.

2. The semiconductor device of claim 1 , wherein the corner structural supports comprise structural billets.

3. The semiconductor device of claim 1 , wherein the corner structural supports comprise copper billets.

4. The semiconductor device of claim 1 , wherein the structural supports comprise a single structural billet in each of four corners of the substrate.

5. The semiconductor device of claim 1 , wherein the structural supports comprise a plurality of structural billets in each of four corners of the substrate.

6. The semiconductor device of claim 1 , wherein the structural supports comprise structural billets which are not part of a conductive pattern for transmitting signals to and from the one or more semiconductor dies.

7. A semiconductor device, comprising:

a substrate comprising:

a dielectric core;

a first conductive layer on a first side of the dielectric core;

a second conductive layer on a second side of the dielectric core;

one or more vias electrically coupling portions of the first conductive layer with portions of the second conductive layer;

first and second opposed surfaces;

solder balls on the first surface and configured to couple the semiconductor device to a host device, and

one or more structural billets, instead of solder balls, on the first surface at each of the corners of the substrate, the one or more structural billets having a higher strength than the solder balls; and

one or more semiconductor dies separate from and coupled to the second surface of the substrate, the substrate configured to transfer signals between the one or more semiconductor dies and the host device.

8. The semiconductor device of claim 7 , wherein the one or more structural billets are formed on a side of the substrate opposite the one or more semiconductor dies.

9. The semiconductor device of claim 7 , wherein the one or more structural billets are formed of copper.

10. The semiconductor device of claim 7 , wherein the one or more structural billets have a circular cross-section.

11. The semiconductor device of claim 7 , wherein the one or more structural billets have one of a rectangular cross-section and an “L”-shaped cross-section.

12. The semiconductor device of claim 7 , wherein the one or more structural billets are not part of a conductive pattern for transmitting signals to and from the one or more semiconductor dies.

13. The semiconductor device of claim 7 , wherein the one or more structural billets are part of a conductive pattern for transmitting signals to and from the one or more semiconductor dies.

14. A semiconductor device, comprising:

a substrate, the substrate comprising:

a dielectric core;

a first conductive layer on a first side of the dielectric core;

a second conductive layer on a second side of the dielectric core;

one or more vias electrically coupling portions of the first conductive layer with portions of the second conductive layer;

first and second opposed surfaces;

solder balls on the first surface of the substrate, the solder balls being in direct contact with the substrate and configured to couple the semiconductor device to a host device, and

structural support means on the first surface of the substrate for structurally supporting the semiconductor device on the host device, the structural support means in direct contact with the substrate and provided at corners of the substrate and having a higher strength than the solder balls; and

one or more semiconductor dies coupled to the second surface of the substrate.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2019
From: LIU, YANGMING; YE, NING; CHIU, CHIN-TIEN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 048598/0860 →
Cited By (1)
US 12,374,658