Variable read method for read time performance improvement of non-volatile memory
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to read the memory cells in a read operation. The control means is also configured to adjust at least one word line read timing and ramping parameter used during the read operation based on an amount of cycling of the memory cells.
1 . A memory apparatus, comprising:
memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states; and
a control means coupled to the plurality of word lines and the memory holes and configured to:
read the memory cells in a read operation, and
adjust, based on an amount of cycling of the memory cells, at least one word line read pre-charge time in which unselected ones of the plurality of word lines are pre-charged and ramp up to a target level and selected ones of the plurality of word lines ramp up to a spike voltage at the target level and back down to a steady state voltage.
2 . The memory apparatus as set forth in claim 1 , wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes, the drain-side select gate transistor of each of the memory holes is connected to one of the plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line, and the control means is further configured to adjust the at least one word line read pre-charge time based on a height of each of the plurality of word lines connected to the memory cells being read in the read operation.
3 . A memory apparatus, comprising:
memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states; and
a control means coupled to the plurality of word lines and the memory holes and configured to:
read the memory cells in a read operation, and
adjust at least one word line read timing and ramping parameter used during the read operation based on an amount of cycling of the memory cells,
wherein the at least one word line read timing and ramping parameter used during the read operation includes at least one word line read pre-charge time in which unselected ones of the plurality of word lines are pre-charged and ramp up to a target level and selected ones of the plurality of word lines ramp up to a spike voltage at the target level and back down to a steady state voltage, the selected ones of the plurality of word lines ramping up to one of a plurality of read compare voltages corresponding to one of the plurality of data states being read during the read operation following the at least one word line read pre-charge time.
4 . The memory apparatus as set forth in claim 3 , wherein the at least one word line read pre-charge time includes a fresh word line read pre-charge time used when the memory cells have been cycled less than a first predetermined cycling threshold and a first word line read pre-charge time used when the memory cells have been cycled more than the first predetermined cycling threshold and less than a second predetermined cycling threshold and a second word line read pre-charge time used when the memory cells have been cycled more than the second predetermined cycling threshold, the amount of cycling corresponding to a count of erase and program operations completed on the memory cells, and the control means is further configured to:
read the memory cells in the read operation using the fresh word line read pre-charge time;
determine whether the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
read the memory cells in the read operation using the first word line read pre-charge time in response to determining the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
determine whether the memory cells have been cycled more than the second predetermined cycling threshold; and
read the memory cells in the read operation using the second word line read pre-charge time in response to determining the memory cells have been cycled more than the second predetermined cycling threshold.
5 . The memory apparatus as set forth in claim 3 , wherein the at least one word line read timing and ramping parameter used during the read operation further includes at least one read word line settling time in which ones of the plurality of word lines and ones of the plurality of bit lines settle.
6 . The memory apparatus as set forth in claim 5 , wherein the at least one word line read pre-charge time includes a fresh word line read pre-charge time used when the memory cells have been cycled less than a first predetermined cycling threshold and a first word line read pre-charge time used when the memory cells have been cycled more than the first predetermined cycling threshold and less than a second predetermined cycling threshold and a second word line read pre-charge time used when the memory cells have been cycled more than the second predetermined cycling threshold, the at least one read word line settling time includes a fresh read word line settling time used when the memory cells have been cycled less than the first predetermined cycling threshold and a first read word line settling time used when the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold, the fresh word line read pre-charge time is longer than the first word line read pre-charge time and the first word line read pre-charge time is longer than the second word line read pre-charge time, the fresh read word line settling time is shorter than the first read word line settling time, the amount of cycling corresponding to a count of erase and program operations completed on the memory cells, and the control means is further configured to:
read the memory cells in the read operation using the fresh word line read pre-charge time and the fresh read word line settling time;
determine whether the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
read the memory cells in the read operation using the first word line read pre-charge time and the first read word line settling time in response to determining the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
determine whether the memory cells have been cycled more than the second predetermined cycling threshold; and
read the memory cells in the read operation using the second word line read pre-charge time in response to determining the memory cells have been cycled more than the second predetermined cycling threshold.
7 . The memory apparatus as set forth in claim 3 , wherein the at least one word line read timing and ramping parameter used during the read operation further includes at least one word line read ramp rate defining a rate at which the plurality of word lines ramp up to the target level during the at least one word line read pre-charge time during the read operation, the at least one read word line read timing and ramping parameter used during the read operation further includes at least one fast read mode word line read pre-charge time in which unselected ones of the plurality of word lines are pre-charged and ramp up to the target level and selected ones of the plurality of word lines ramp up to the spike voltage at the target level and back down to the steady state voltage, the selected ones of the plurality of word lines ramping up to one of plurality of read compare corresponding to the one of the plurality of data states being read during a fast read operation.
8 . A controller in communication with a memory apparatus including memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the controller configured to:
instruct the memory apparatus to read the memory cells in a read operation; and
adjust, based on an amount of cycling of the memory cells, at least one word line read pre-charge time in which unselected ones of the plurality of word lines are pre-charged and ramp up to a target level and selected ones of the plurality of word lines ramp up to a spike voltage at the target level and back down to a steady state voltage.
9 . The controller as set forth in claim 8 , wherein the selected ones of the plurality of word lines ramp up to one of a plurality of read compare voltages corresponding to one of the plurality of data states being read during the read operation following the at least one word line read pre-charge time.
10 . The controller as set forth in claim 9 , wherein the at least one word line read pre-charge time includes a fresh word line read pre-charge time used when the memory cells have been cycled less than a first predetermined cycling and a first word line read pre-charge time used when the memory cells have been cycled more than the first predetermined cycling threshold and less than a second predetermined cycling threshold and a second word line read pre-charge time used when the memory cells have been cycled more than the second predetermined cycling threshold, the amount of cycling corresponding to a count of erase and program operations completed on the memory cells, and the controller is further configured to:
instruct the memory apparatus to read the memory cells in the read operation using the fresh word line read pre-charge time;
determine whether the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
instruct the memory apparatus to read the memory cells in the read operation using the first word line read pre-charge time in response to determining the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
determine whether the memory cells have been cycled more than the second predetermined cycling threshold; and
instruct the memory apparatus to read the memory cells in the read operation using the second word line read pre-charge time in response to determining the memory cells have been cycled more than the second predetermined cycling threshold.
11 . The controller as set forth in claim 9 , wherein the controller is further configured to adjust at least one read word line settling time in which one or more of the plurality of word lines and one or more of the plurality of bit lines settle.
12 . The controller as set forth in claim 11 , wherein the at least one word line read pre-charge time includes a fresh word line read pre-charge time used when the memory cells have been cycled less than a first predetermined cycling and a first word line read pre-charge time used when the memory cells have been cycled more than the first predetermined cycling threshold and less than a second predetermined cycling threshold and a second word line read pre-charge time used when the memory cells have been cycled more than the second predetermined cycling threshold, the at least one read word line settling time includes a fresh read word line settling time used when the memory cells have been cycled less than the first predetermined cycling threshold and a first read word line settling time used when the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold, the fresh word line read pre-charge time is longer than the first word line read pre-charge time and the first word line read pre-charge time is longer than the second word line read pre-charge time, the fresh read word line settling time is shorter than the first read word line settling time, the amount of cycling corresponding to a count of erase and program operations completed on the memory cells, and the controller is further configured to:
instruct the memory apparatus to read the memory cells in the read operation using the fresh word line read pre-charge time and the fresh read word line settling time;
determine whether the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
instruct the memory apparatus to read the memory cells in the read operation using the first word line read pre-charge time and the first read word line settling time in response to determining the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
determine whether the memory cells have been cycled more than the second predetermined cycling threshold; and
instruct the memory apparatus to read the memory cells in the read operation using the second word line read pre-charge time in response to determining the memory cells have been cycled more than the second predetermined cycling threshold.
13 . The controller as set forth in claim 9 , wherein the controller is further configured to adjust at least one word line read ramp rate defining a rate at which the plurality of word lines ramp up to the target level during the at least one word line read pre-charge time during the read operation, wherein the at least one word line read pre-charge time includes at least one fast read mode word line read pre-charge time in which unselected ones of the plurality of word lines are pre-charged and ramp up to the target level and selected ones of the plurality of word lines ramp up to the spike voltage at the target level and back down to the steady state voltage, the selected ones of the plurality of word lines ramping up to one of plurality of read compare corresponding to the one of the plurality of data states being read during a fast read operation.
14 . A method of operating a memory apparatus including memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the method comprising the steps of:
reading the memory cells in a read operation; and
adjusting, based on an amount of cycling of the memory cells, at least one word line read pre-charge time in which unselected ones of the plurality of word lines are pre-charged and ramp up to a target level and selected ones of the plurality of word lines ramp up to a spike voltage at the target level and back down to a steady state voltage.
15 . The method as set forth in claim 14 , wherein the selected ones of the plurality of word lines ramp up to one of a plurality of read compare voltages corresponding to one of the plurality of data states being read during the read operation following the at least one word line read pre-charge time.
16 . The method as set forth in claim 15 , wherein the at least one word line read pre-charge time includes a fresh word line read pre-charge time used when the memory cells have been cycled less than a first predetermined cycling threshold and a first word line read pre-charge time used when the memory cells have been cycled more than the first predetermined cycling threshold and less than a second predetermined cycling threshold and a second word line read pre-charge time used when the memory cells have been cycled more than the second predetermined cycling threshold, the amount of cycling corresponding to a count of erase and program operations completed on the memory cells, and the method further includes the steps of:
reading the memory cells in the read operation using the fresh word line read pre-charge time;
determining whether the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
reading the memory cells in the read operation using the first word line read pre-charge time in response to determining the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
determining whether the memory cells have been cycled more than the second predetermined cycling threshold; and
reading the memory cells in the read operation using the second word line read pre-charge time in response to determining the memory cells have been cycled more than the second predetermined cycling threshold.
17 . The method as set forth in claim 15 , further comprising adjusting at least one read word line settling time in which one or more of the plurality of word lines and one or more of the plurality of bit lines settle.
18 . The method as set forth in claim 17 , wherein the at least one word line read pre-charge time includes a fresh word line read pre-charge time used when the memory cells have been cycled less than a first predetermined cycling threshold and a first word line read pre-charge time used when the memory cells have been cycled more than the first predetermined cycling threshold and less than a second predetermined cycling threshold and a second word line read pre-charge time used when the memory cells have been cycled more than the second predetermined cycling threshold, the at least one read word line settling time includes a fresh read word line settling time used when the memory cells have been cycled less than the first predetermined cycling threshold and a first read word line settling time used when the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold, the fresh word line read pre-charge time is longer than the first word line read pre-charge time and the first word line read pre-charge time is longer than the second word line read pre-charge time, the fresh read word line settling time is shorter than the first read word line settling time, the amount of cycling corresponding to a count of erase and program operations completed on the memory cells, and the method further includes the steps of:
reading the memory cells in the read operation using the fresh word line read pre-charge time and the fresh read word line settling time;
determining whether the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
reading the memory cells in the read operation using the first word line read pre-charge time and the first read word line settling time in response to determining the memory cells have been cycled more than the first predetermined cycling threshold and less than the second predetermined cycling threshold;
determining whether the memory cells have been cycled more than the second predetermined cycling threshold; and
reading the memory cells in the read operation using the second word line read pre-charge time in response to determining the memory cells have been cycled more than the second predetermined cycling threshold.
19 . The method as set forth in claim 15 , further comprising adjusting at least one word line read ramp rate defining a rate at which the plurality of word lines ramp up to the target level during the at least one word line read pre-charge time during the read operation, wherein the at least one word line read pre-charge time includes at least one fast read mode word line read pre-charge time in which unselected ones of the plurality of word lines are pre-charged and ramp up to the target level and selected ones of the plurality of word lines ramp up to the spike voltage at the target level and back down to the steady state voltage, the selected ones of the plurality of word lines ramping up to one of plurality of read compare corresponding to the one of the plurality of data states being read during a fast read operation.
20 . The method as set forth in claim 14 , wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes, the drain-side select gate transistor of each of the memory holes is connected to one of the plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line, and the method further includes the step of adjusting the at least one word line read timing and ramping parameter used during the read operation based on a height of each of the plurality of word lines connected to the memory cells being read in the read operation.