IP Library Granted Patent US 10,229,751
Granted Patent B2
US 10,229,751 · App. 15/583,747 · Granted Mar 12, 2019

Storage system and method for bad block recycling

Inventors: Dudy Avraham (Even Yehuda, IL); Ran Zamir (Ramat Gan, IL); Idan Alrod (Herzliya, IL); Eran Sharon (Rishon Lezion, IL)
Assignee: Western Digital Technologies, Inc.
G11C29/765G11C16/14G11C29/12G11C2029/1202
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Quick Facts
Patent No.
US 10,229,751
App. No.
15/583,747
Granted
Mar 12, 2019
Kind
B2
Abstract

A storage system is provided comprising a controller and a memory. The controller is configured to identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline; identify which wordlines in the at least two physical blocks of memory are defective; and create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.

Claims (37)

1. A storage system comprising:

a memory comprising a plurality of physical blocks of memory; and

a controller in communication with the memory, wherein the controller is configured to:

identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline;

identify which wordlines in the at least two physical blocks of memory are defective; and

create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.

2. The storage system of claim 1 , wherein the memory comprises a plurality of memory dies organized in a plurality of planes, and wherein the at least two physical blocks of memory are from a same plane.

3. The storage system of claim 1 , wherein the controller is further configured to, for each of the at least two physical blocks of memory, create the logical block by selecting wordlines up to a defective wordline area.

4. The storage system of claim 3 , wherein the controller is further configured to erase wordlines subsequent to the defective wordline area in the at least two physical blocks of memory.

5. The storage system of claim 1 , wherein the controller is further configured to create the logical block by selecting wordlines preceding the defective wordline area in one of the at least two physical blocks of memory and by selecting wordlines subsequent to the defective wordline area in another one of the at least two physical blocks of memory.

6. The storage system of claim 5 , wherein the controller is further configured to write random data preceding the defective wordline area in the another one of the at least two physical blocks of memory.

7. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

8. The storage system of claim 1 , wherein the storage system is embedded in a host.

9. The storage system of claim 1 , wherein the storage system is removably connected to a host.

10. A storage system comprising:

a memory comprising a plurality of physical blocks of memory; and

a controller in communication with the memory, wherein the controller is configured to:

identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline;

identify which wordlines in the at least two physical blocks of memory are defective; and

create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory;

wherein the controller is configured to identify the at least two physical blocks of memory by determining that a number of non-defective wordlines in the at least two physical blocks of memory sum up to at least a number of wordlines needed to create a logical block.

11. A method for bad block recycling, the method comprising:

determining a bit error rate for each of a plurality of bad blocks of memory in a storage system; and

writing data N number of times, once in each of N number of bad blocks having a same bit error rate, wherein N>1 and is based on the bit error rate and increases as the bit error rate increases.

12. The method of claim 11 , wherein the memory comprises a three-dimensional memory.

13. The method of claim 11 , wherein the storage system is embedded in a host.

14. The method of claim 11 , wherein the storage system is removably connected to a host.

15. A storage system comprising:

a memory comprising a plurality of physical blocks of memory;

means for identifying at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline;

means for identifying which wordlines in the at least two physical blocks of memory are defective; and

means for creating a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.

16. The storage system of claim 15 further comprising means for identifying the at least two physical blocks of memory by determining that a number of non-defective wordlines in the at least two physical blocks of memory sum up to at least a number of wordlines needed to create the logical block.

17. The storage system of claim 15 further comprising means for writing data redundantly in N number of bad blocks having a same bit error rate, wherein N is based on the bit error rate and increases as the bit error rate increases.

18. The storage system of claim 15 , wherein the memory comprises a three-dimensional memory.

19. The storage system of claim 15 , wherein the storage system is embedded in a host.

20. The storage system of claim 15 , wherein the storage system is removably connected to a host.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2017
From: AVRAHAM, DUDY; ZAMIR, RAN; ALROD, IDAN; SHARON, ERAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 042231/0251 →
Continuity (1)
Related Publication 20180315487A1 · Nov 1, 2018
Cited By (2)
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