Implementing enhanced performance with read before write to phase change memory
View Patent ↗A method and apparatus are provided for implementing enhanced performance with read before write to phase-change-memory. Each write to PCM is preceded by a read and a calculation to discover a location of any bad bits. The write data is converted to a format that can be corrected for a given number of previously undiscovered bit errors, and the writes are unverified.
1. A method for implementing data write to phase-change-memory (PCM) in a system including phase-change-memory (PCM); a phase-change-memory (PCM) interface control coupled to said phase-change-memory (PCM); a controller coupled to said phase-change-memory (PCM) interface control for implementing data write to the phase-change-memory (PCM); said controller using said phase-change-memory (PCM) control code performing the steps of said method comprising:
starting a data write;
reading a group of PCM cells of the phase-change-memory (PCM) before writing to the group of cells and identifying any defective cells;
responsive to the identified defective cells, performing a data write for data being written to the PCM using data encoding to avoid writing to the identified defective cells; and
responsive to performing the data write, maintaining the written data without error checking the data write and without performing another data write for correcting any newly arising bit errors with the data write.
2. The method for implementing data write as recited in claim 1 wherein starting the data write includes receiving a write request.
3. The method for implementing data write as recited in claim 1 wherein reading the group of PCM cells before writing to the group of cells to identify any defective cells before performing the data write includes performing a calculation to discover a location of each bad bit.
4. The method for implementing data write as recited in claim 3 includes reading existing user data for the group of PCM cells before writing to the group of cells, and comparing the existing user data against error correcting coding bit information with the existing user data run through a BCH decoder.
5. The method for implementing data write as recited in claim 4 wherein comparing the user data against error correcting coding bit information includes comparing user data against a selected one of an Error Correcting Code (ECC) bits and Cyclic Redundancy Check (CRC) bits to discover the location of each bad bit.
6. The method for implementing data write as recited in claim 1 wherein responsive to the identified defective cells, performing a data write for data being written to the PCM includes converting the data being written to a format enabling correction of a set number of bit errors using selected error correcting codes to protect data integrity.
7. An apparatus for implementing data write to phase-change-memory (PCM) comprising:
a phase-change-memory (PCM);
a phase-change-memory (PCM) interface control coupled to said phase-change-memory (PCM);
a controller coupled to said phase-change-memory (PCM) interface control for implementing data write to the phase-change-memory (PCM);
phase-change-memory (PCM) control code coupled to said controller;
said controller using said phase-change-memory (PCM) control code performing the steps:
starting a data write;
reading a group of PCM cells of the phase-change-memory (PCM) before writing to the group of cells and identifying any defective cells;
responsive to the identified defective cells, performing a data write for data being written to the PCM using data encoding to avoid writing to the identified defective cells; and
responsive to performing the data write, maintaining the written data without error checking the data write and without performing another data write for correcting any newly arising bit errors with the data write.
8. The apparatus for implementing data write as recited in claim 7 includes said control code stored on a non-transitory computer readable medium.
9. The apparatus for implementing data write as recited in claim 7 includes said controller receiving a write request and starting the data write.
10. The apparatus for implementing data write as recited in claim 7 wherein said controller reading PCM cells before performing the data write includes said controller performing a calculation to discover a location of each bad bit.
11. The apparatus for implementing data write as recited in claim 10 includes said controller reading existing user data for the group of PCM cells before writing to the group of cells, and comparing the existing user data against error correcting coding bit information with the existing user data run through a BCH decoder.
12. The apparatus as recited in claim 11 wherein said controller comparing the existing user data against error correcting coding bit information with the existing user data run through a BCH decoder and further includes said controller comparing existing user data against a selected one of an Error Correcting Code (ECC) bits and Cyclic Redundancy Check (CRC) bits to discover the location of each bad bit.
13. The apparatus as recited in claim 7 wherein said controller responsive to the identified defective cells, performing a data write for data being written to the PCM includes said controller converting the data being written to a format enabling correction of a set number of bit errors using selected error correcting codes to protect data integrity.
14. A data storage device comprising:
a phase-change-memory (PCM);
a phase-change-memory (PCM) interface control coupled to said phase-change-memory (PCM);
a controller coupled to said phase-change-memory (PCM) interface control for implementing data write to the phase-change-memory (PCM);
phase-change-memory (PCM) control code coupled to said controller;
said controller using said phase-change-memory (PCM) control code performing the steps:
starting a data write;
reading a group of PCM cells of the phase-change-memory (PCM) before writing to the group of cells and identifying any defective cells;
responsive to the identified defective cells, performing a data write for data being written to the PCM using data encoding to avoid writing to the identified defective cells; and
responsive to performing the data write, maintaining the written data without error checking the data write and without performing another data write for correcting any newly arising bit errors with the data write.
15. The data storage device as recited in claim 14 , includes said control code stored on a non-transitory computer readable medium.
16. The data storage device as recited in claim 14 , wherein said controller reading a group of PCM cells to identify any defective cells includes said controller reading existing user data for the group of PCM cells before writing to the group of cells, and comparing the existing user data against error correcting coding bit information with the existing user data run through a BCH decoder.
17. The data storage device as recited in claim 16 , wherein said controller comparing the existing user data against error correcting coding bit information with the existing user data run through a BCH decoder and further includes said controller comparing existing user data against a selected one of an Error Correcting Code (ECC) bits and Cyclic Redundancy Check (CRC) bits to discover the location of each bad bit.