IP Library Granted Patent US 11,204,833
Granted Patent B1
US 11,204,833 · App. 16/906,961 · Granted Dec 21, 2021

NVM endurance group controller using shared resource architecture

Inventors: Amir Rozen (Rishon Lezion, IL); Shay Benisty (Beer Sheva, IL); Vitali Linkovsky (Beer Sheva, IL)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F11/1068G06F11/076G06F11/1044G06F11/3037
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Quick Facts
Patent No.
US 11,204,833
App. No.
16/906,961
Granted
Dec 21, 2021
Kind
B1
Abstract

A method and apparatus for allocation of back-end (BE) logic resources between NVM sets. When a controller detects that an NVM set is in an idle state, it deallocates the BE logic from the originally assigned NVM set and provides the BE logic resource to another NVM set. An NVM set controller matrix maps interconnections between the BE logic resource and the new NVM set to enable use of the BE logic resource and the new NVM set. When a new command arrives for the originally assigned NVM set, the BE logic resources is re-allocated to the originally assigned NVM set.

Claims (58)

1. A data storage device, comprising:

one or more non-volatile memory (NVM) devices each comprising a plurality of NVM sets;

a controller coupled to the one or more NVM devices, the controller comprising an NVM set controller (NVMS SC), and a plurality of back-end (BE) logics, each BE logic correlating to a respective one of the plurality of NVM sets, wherein the controller is configured to carry out a method for sharing NVM set resources, the method comprising:

detecting when a first NVM set of the plurality of NVM sets is in an idle state; and

allocating a first BE logic corresponding to the first NVM set to a second NVM set.

2. The data storage device of claim 1 , further comprising an NVM set controller matrix.

3. The data storage device of claim 2 , wherein the method further comprises configuring the NVM set controller matrix to map the NVM set controller to use the first BE logic with the second NVM set.

4. The data storage device of claim 3 , wherein the first BE logic comprises one of a CPU, an error correction code (ECC) engine, a flash interface, and a data-path part.

5. The data storage device of claim 1 , wherein the controller further comprises a threshold counter, and wherein the method further comprises starting the threshold counter when in an idle state, and detecting when the counter reaches a threshold value.

6. The data storage device of claim 5 , wherein detecting when the first NVM set is in an idle state comprises detecting when a command to the first NVM set is complete, and detecting that there are no additional commands following the command.

7. The data storage device of claim 1 , wherein the method further comprises:

receiving a command for the first NVM set; and

deallocating the first BE logic from the second NVM set.

8. The data storage device of claim 7 , wherein the method further comprises

determining that an additional command is being fetched for the first BE logic to process for the second NVM set; and

re-routing the additional command to a different BE logic from the first BE logic to process for the second NVM set.

9. A data storage device comprising:

one or more non-volatile memory (NVM) devices, each comprising a plurality of NVM sets; and

a controller coupled to the one or more NVM devices comprising an NVM set controller, a plurality of back-end (BE) logics, each BE logic correlating to a respective one of the plurality of NVM sets, wherein the controller is configured to carry out a method for sharing NVM set resources, the method comprising:

allocating a first BE logic from a first NVM set to process commands for a second NVM set; and

detecting that a first command has arrived for the first BE logic, the first command pertaining to data on the first NVM set.

10. The data storage device of claim 9 , wherein the method further comprises:

detecting an additional command for the second NVM set; and

ceasing providing the additional command for the second NVM set to the first BE logic.

11. The data storage device of claim 10 , wherein the method further comprises:

determining, by the NVM set controller, that there are no further commands to be fetched for the second NVM set to be processed by the first BE logic; and

determining, by the NVM set controller, whether or not to cancel execution of the additional command for the second NVM set on the first BE logic.

12. The data storage device of claim 11 , wherein the method further comprises:

determining that the execution of the additional command for the second NVM set on the first BE logic is not to be canceled;

postponing execution of the first command;

executing the additional command on the first BE logic; and

deallocating the first BE logic from the second NVM set to the first NVM set.

13. The data storage device of claim 11 , wherein the method further comprises:

determining that the execution of the additional command for the second NVM set on the first BE logic is to be canceled;

deallocating the first BE logic from the second NVM set to the first NVM set; and

re-routing the additional command to a third BE logic of the plurality of BE logics to be processed for the second NVM set.

14. The data storage device of claim 13 , further comprises an NVM set controller matrix, and wherein the method further comprises:

configuring the set controller matrix such that the third BE logic processes commands for the second NVM set.

15. The data storage device of claim 14 , wherein the method further comprises:

detecting that a third NVM set correlated to the third BE logic is in an idle state;

deallocating the third BE logic from the third NVM set; and

allocating the third BE logic to the second NVM set.

16. The data storage device of claim 11 , wherein the first BE logic comprises one of a CPU, an ECC engine, a flash interface, and a data-path part.

17. A system for storing data, the system comprising:

a non-volatile memory (NVM) means comprising a plurality of memory devices; and

a controller means, the controller means comprising:

a plurality of back-end (BE) logic means coupled to the NVM means;

an NVM set controller means defining one or more NVM sets;

an NVM set controller matrix means defining logical connection between each one of the plurality of BE logic means and each one of the one or more NVM sets; and

wherein the controller is configured to carry out a method for sharing NVM set resources, the method comprising:

detecting when a first NVM set of the one or more NVM sets is in an idle state; and

allocating a first BE logic means corresponding to the first NVM set to a second NVM set.

18. The system of claim 17 , wherein the controller means is configured to carry out a method for sharing NVM set resources, the method comprising:

detecting that a first command has arrived for the first BE logic means, the first command pertaining to data on the first NVM set; and

deallocating the first BE logic means from the second NVM set to the first NVM set.

19. The system of claim 18 , wherein the deallocating further comprises:

determining, by the NVM set controller, that there are no further commands to be fetched for the second NVM set to be processed by the first BE logic; and

determining, by the NVM set controller means, whether or not to cancel execution of an additional command for the second NVM set on the first BE logic.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2020
From: ROZEN, AMIR; BENISTY, SHAY; LINKOVSKY, VITALI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053004/0224 →
Cited By (1)
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