Storage system and method for direct quad-level cell (QLC) programming
A storage system and method for direct quad-level cell (QLC) programming are provided. In one example, a controller of the storage system is configured to create codewords for lower, middle, and upper pages of data; program the codewords in the memory of the storage system using a triple-level cell programming operation; read the programming of the codewords for the lower, middle, and upper pages of data in the memory; create a codeword for a top page of data; and program the codeword in the memory.
1. A storage system comprising:
a memory; and
a controller configured to:
create codewords for lower, middle, and upper pages of data;
program the codewords for the lower, middle, and upper pages of data in the memory using a triple-level cell programming operation;
read the programming of the codewords for the lower, middle, and upper pages of data in the memory;
create a codeword for a top page of data; and
program the codeword for the top page of data in the memory using the read lower, middle, and upper pages of data.
2. The storage system of claim 1 , wherein the codewords for the lower, middle, and upper pages of data are programmed with a balanced 2-3-2 grey code mapping.
3. The storage system of claim 2 , wherein programing the codeword for the top page of data in the memory induces a quad-level cell (QLC) distribution with 2-3-2-8 grey code mapping.
4. The storage system of claim 1 , wherein the read data is retrieved without using error correction.
5. The storage system of claim 1 , wherein the lower, middle and upper pages are read from the memory array without retrieving them from a write buffer in the controller.
6. The storage system of claim 1 , wherein the codewords are created by encoding the lower, middle; and upper pages of data with error correction code parity bits.
7. The storage system of claim 6 , wherein the codeword for the top page of data is created by encoding the top page of data with more error correction code parity bits than the lower, middle, and upper pages of data.
8. The storage system of claim 1 , wherein foggy data is retrieved using a low complexity ECC decoder on the memory die or on a CMOS die bonded to the memory die (CbA).
9. In a storage system comprising a memory and a controller, a method comprising:
computing first and second parity bits for lower, middle, and upper pages of data;
programming the lower, middle, and upper pages of data with the first parity bits using a triple-level cell programming operation;
reading the programming of the lower, middle, and upper pages of data in the memory; and
programing a top page of data in the memory using the read lower, middle, and upper pages of data.
10. The method of claim 9 , wherein the lower, middle, and upper pages of data are programmed with a balanced 2-3-2 grey code mapping.
11. The method of claim 10 , wherein programing the top page of data in the memory induces a quad-level cell (QLC) distribution with 2-3-2-8 grey code mapping.
12. The method of claim 9 , wherein the top page of data is programmed with the first parity bits and an exclusive-OR signature of the second parity bits.
13. The method of claim 9 , wherein the lower, middle and upper pages are read from the memory array without retrieving them from a write buffer in the controller.
14. The method of claim 1 , wherein the top page comprises a smaller payload than the lower, middle, and upper pages.
15. A storage system comprising:
a memory;
means for encoding each of lower, middle, upper, and top pages of data with an amount of error correction code parity bits that is proportional to a number of transition in each page;
means for programming the lower, middle, and upper pages of data in the memory using a triple-level cell programming operation;
means for reading the programming of the lower, middle, and upper pages of data in the memory; and
means for programing the top page of data in the memory using the read lower, middle, and upper pages of data.
16. The storage system of claim 15 , wherein the lower, middle, and upper pages of data are programmed with a balanced 2-3-2 grey code mapping.
17. The storage system of claim 16 , wherein programing the top page of data in the memory induces a quad-level cell (QLC) distribution with 2-3-2-8 grey code mapping.
18. The storage system of claim 15 , wherein a number of error correction code parity bits in the top page that exceed a number of error correction code columns in a wordline are divided into a first part and a second part, wherein the first part fits within the top page, and wherein the second part is stored as part of the lower, middle, and upper pages.
19. The storage system of claim 15 , further comprising means for storing the same data on the top page, but having its ECC redundancy spill over to the other pages.
20. The storage system of claim 15 , wherein the lower, middle and upper pages are read from the memory array without retrieving them from a write buffer in a controller of the storage system.