Data storage device with dynamic mapping of low-density parity check (LDPC) engines
The devices, methods, and apparatuses of the present disclosure address a lack of parallelism in a typical approach by eliminating the static mapping of the two or more low-density parity check (LDPC) engines to a plurality of flash controllers. The devices, methods, and apparatuses of the present disclosure include a dynamic LDPC mapping to the plurality of flash controllers.
1. A data storage device comprising:
a memory including
a plurality of memory dies, and
support circuitry configured to support memory operations at the plurality of memory dies, the support circuitry including a plurality of low-density parity check (LDPC) engines and a plurality of flash controllers (FCs), each of the plurality of FCs corresponding to one of the plurality of memory dies; and
a data storage controller including an interface and a flash translation layer (FTL), the data storage controller is configured to control the interface to output the memory operations to the memory using the FTL and a bus,
wherein the support circuitry is configured to dynamically map the plurality of LDPC engines to the plurality of FCs.
2. The data storage device of claim 1 , wherein the support circuitry further includes a scheduler and a dynamic allocator, and
wherein the support circuitry is further configured to:
receive, with the scheduler, the memory operations from the interface,
add, with the scheduler, required information to the memory operations, and
store, with the dynamic allocator, the memory operations in a priority queue of the dynamic allocator based on priority information.
3. The data storage device of claim 2 , wherein the support circuitry further includes a re-organizer, and
wherein, to dynamically map the plurality of LDPC engines to the plurality of FCs, the support circuitry is further configured to:
dynamically allocate, with the dynamic allocator, the memory operations that are stored in the priority queue to the plurality of LDPC engines,
perform, with the plurality of LDPC engines, parity checking and error correction on the memory operations that have been dynamically allocated to the plurality of LDPC engines,
store, with the re-organizer, the memory operations that have been parity checked and error corrected in a plurality of memory buffers, each memory buffer corresponding to one of the plurality of FCs,
retrieve, with the each of the plurality of FCs, a memory operation that is stored in one of the plurality of memory buffers, and
perform, with the each of the plurality of FCs, the memory operation at the corresponding one of the plurality of memory dies.
4. The data storage device of claim 3 , wherein the support circuitry is further configured to:
receive, with the dynamic allocator, feedback information from the plurality of LDPC engines, and
dynamically allocate, with the dynamic allocator, the memory operations that are stored in the priority queue to the plurality of LDPC engines based on the feedback information.
5. The data storage device of claim 4 , wherein the feedback information indicates a load level of each of the plurality of LDPC engines.
6. The data storage device of claim 3 , wherein the memory operation is a read operation, and wherein the support circuitry is further configured to:
transfer, with the each of the plurality of FCs, data that is read from the corresponding one of the plurality of memory dies to a second one of the plurality of memory buffers, and
output, with the re-organizer, a location of the corresponding one of the plurality of memory dies to the dynamic allocator.
7. The data storage device of claim 6 , wherein the support circuitry is further configured to:
dynamically allocate, with the dynamic allocator, the data that are stored in the second one of the plurality of memory buffers to the plurality of LDPC engines,
perform, with the plurality of LDPC engines, decoding of the data that has been dynamically allocated to the plurality of LDPC engines, and
output the data that is decoded to a plurality of latches.
8. A method comprising:
outputting, with a data storage controller including an interface and a flash translation layer (FTL), memory operations to a memory including a plurality of memory dies and support circuitry including a plurality of low-density parity check (LDPC) engines and a plurality of flash controllers (FCs), each of the plurality of FCs corresponding to one of the plurality of memory dies; and
dynamically mapping, with the support circuitry, the plurality of LDPC engines to the plurality of FCs.
9. The method of claim 8 , further comprising:
receiving the memory operations from the interface;
adding required information to the memory operations; and
storing the memory operations in a priority queue based on priority information.
10. The method of claim 9 , wherein the support circuitry further includes a plurality of memory buffers, and
wherein dynamically mapping the plurality of LDPC engines to the plurality of FCs further includes:
dynamically allocating the memory operations that are stored in the priority queue to the plurality of LDPC engines,
performing parity checking and error correction on the memory operations that have been dynamically allocated to the plurality of LDPC engines,
storing the memory operations that have been parity checked and error corrected in the plurality of memory buffers, each memory buffer corresponding to one of the plurality of FCs,
retrieving, with the each of the plurality of FCs, a memory operation that is stored in one of the plurality of memory buffers, and
performing, with the each of the plurality of FCs, the memory operation at the corresponding one of the plurality of memory dies.
11. The method of claim 10 , further comprising:
receiving feedback information from the plurality of LDPC engines; and
dynamically allocating the memory operations that are stored in the priority queue to the plurality of LDPC engines based on the feedback information.
12. The method of claim 11 , wherein the feedback information indicates a load level of each of the plurality of LDPC engines.
13. The method of claim 10 , wherein the memory operation is a read operation, the method further comprising:
transferring data that is read from the corresponding one of the plurality of memory dies to a second one of the plurality of memory buffers.
14. The method of claim 13 , further comprising:
dynamically allocating the data that are stored in the second one of the plurality of memory buffers to the plurality of LDPC engines;
decoding, with the plurality of LDPC engines, the data that has been dynamically allocated to the plurality of LDPC engines; and
outputting the data that is decoded to a plurality of latches.
15. An apparatus comprising:
means for outputting memory operations to a memory including a plurality of memory dies and support circuitry including a plurality of low-density parity check (LDPC) engines and a plurality of flash controllers (FCs), each of the plurality of FCs corresponding to one of the plurality of memory dies; and
means for dynamically mapping the plurality of LDPC engines to the plurality of FCs.
16. The apparatus of claim 15 , further comprising:
means for adding required information to the memory operations; and
means for storing the memory operations in a priority queue based on priority information.
17. The apparatus of claim 16 , wherein the support circuitry further includes a plurality of memory buffers, and
wherein the means for dynamically mapping the plurality of LDPC engines to the plurality of memory dies further includes:
means for dynamically allocating the memory operations that are stored in the priority queue to the plurality of LDPC engines,
means for performing parity checking and error correction on the memory operations that have been dynamically allocated to the plurality of LDPC engines,
means for storing the memory operations that have been parity checked and error corrected in the plurality of memory buffers, each memory buffer corresponding to one of the plurality of FCs,
means for retrieving a memory operation that is stored in one of the plurality of memory buffers, and
means for performing the memory operation at the corresponding one of the plurality of memory dies.
18. The apparatus of claim 17 , further comprising:
means for receiving feedback information from the plurality of LDPC engines; and
means for dynamically allocating the memory operations that are stored in the priority queue to the plurality of LDPC engines based on the feedback information.
19. The apparatus of claim 17 , wherein the memory operation is a read operation, the method further comprising:
means for transferring data that is read from the corresponding one of the plurality of memory dies to a second one of the plurality of memory buffers.
20. The apparatus of claim 19 , further comprising:
means for dynamically allocating the data that are stored in the second one of the plurality of memory buffers to the plurality of LDPC engines;
means for decoding, with the plurality of LDPC engines, the data that has been dynamically allocated to the plurality of LDPC engines; and
means for outputting the data that is decoded to a plurality of latches.